Wayne Lin 320eca62fe drm/amd/display: Add otg vertical interrupt0 support in DCN1.0 ... [Why & How] On DCN1.0, need otg vertical line interrupt to get appropriate timing to achieve specific feature request. Add otg vertical interrupt0 support for registers which operation is vertical sensitive. Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-02-09 15:29:02 -05:00
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acp	drm: amd/acp: fix broken menu structure	2020-03-13 11:52:35 -04:00
amdgpu	drm/amdgpu: Add otg vertical IRQ Source	2021-02-09 15:28:55 -05:00
amdkfd	drm/amdkfd: Get unique_id dynamically v2	2021-02-09 15:27:28 -05:00
display	drm/amd/display: Add otg vertical interrupt0 support in DCN1.0	2021-02-09 15:29:02 -05:00
include	drm/amdgpu: add SMUIO 11.0.6 register headers	2021-02-09 15:28:11 -05:00
pm	drm/amd/pm/swsmu: unify the init soft gpu metrics function	2021-02-09 15:28:42 -05:00