319711f982
If the divider used to get the pixel-clock is small, the granularity of the frequencies possible for the pixel-clock is quite coarse. E.g. requesting a pixel-clock of 65MHz with a sys_clk of 132MHz results in the divider being set to 3 ending up with 44MHz. By preferring the doubled sys_clk as base, the divider instead ends up as 5 yielding a pixel-clock of 52.8Mhz, which is a definite improvement. While at it, clamp the divider so that it does not overflow in case it gets big. Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180824092458.13165-2-peda@axentia.se |
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| .. | ||
| atmel_hlcdc_crtc.c | ||
| atmel_hlcdc_dc.c | ||
| atmel_hlcdc_dc.h | ||
| atmel_hlcdc_output.c | ||
| atmel_hlcdc_plane.c | ||
| Kconfig | ||
| Makefile | ||