linux/drivers/gpu
Marta Lofstedt 3164888a40 drm/i915: Increase poll time for BDW FCLK_DONE
During IGT testing it has been shown that the specification
defined polling time of 1 us for FCLK_DONE, is sometimes not
enough. The issue is still reproducible while disabling
C-states through the PM QoS framework and also while disabling
preemtion. From this the most plausible explanation is that the
issue is due to a firmware flaw.
As a workaround, it is better to wait a little bit longer for
the FCLK_DONE to come around, than to leave with an DRM_ERROR
and having FCLK_DONE at a randome time after.
While spinning a list of igt tests prone to reproduce the issue
the FCLK_DONE poll failed at approximately 2% of the invocations
of the bdw_set_cdclk function. The longest poll time during this
testing was measured to ~7us. So, the suggested new poll time of
100us is on the safe side.

v2: Added more documentation about investigations done.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102243
Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170908132829.6312-1-marta.lofstedt@intel.com
2017-09-12 12:19:57 +03:00
..
drm drm/i915: Increase poll time for BDW FCLK_DONE 2017-09-12 12:19:57 +03:00
host1x drm/tegra: Changes for v4.14-rc1 2017-08-21 17:37:33 +10:00
ipu-v3 drm: Convert to using %pOF instead of full_name 2017-07-26 13:45:06 +02:00
vga sched/wait: Rename wait_queue_t => wait_queue_entry_t 2017-06-20 12:18:27 +02:00
Makefile