forked from Minki/linux
63a293e000
Some PRM functions will need to be called by the hwmod code early in kernel init. To handle this, split the PRM initialization code into early and late phases. The early init is handled via mach-omap2/io.c, while the late init is handled by subsys_initcall(). Signed-off-by: Paul Walmsley <paul@pwsan.com>
421 lines
12 KiB
C
421 lines
12 KiB
C
/*
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* OMAP3xxx PRM module functions
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*
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* Copyright (C) 2010-2012 Texas Instruments, Inc.
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* Copyright (C) 2010 Nokia Corporation
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* Benoît Cousson
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* Paul Walmsley
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* Rajendra Nayak <rnayak@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include "common.h"
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#include <plat/cpu.h>
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#include "vp.h"
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#include "powerdomain.h"
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#include "prm3xxx.h"
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#include "prm2xxx_3xxx.h"
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#include "cm2xxx_3xxx.h"
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#include "prm-regbits-34xx.h"
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static const struct omap_prcm_irq omap3_prcm_irqs[] = {
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OMAP_PRCM_IRQ("wkup", 0, 0),
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OMAP_PRCM_IRQ("io", 9, 1),
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};
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static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
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.ack = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
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.mask = OMAP3_PRM_IRQENABLE_MPU_OFFSET,
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.nr_regs = 1,
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.irqs = omap3_prcm_irqs,
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.nr_irqs = ARRAY_SIZE(omap3_prcm_irqs),
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.irq = 11 + OMAP_INTC_START,
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.read_pending_irqs = &omap3xxx_prm_read_pending_irqs,
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.ocp_barrier = &omap3xxx_prm_ocp_barrier,
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.save_and_clear_irqen = &omap3xxx_prm_save_and_clear_irqen,
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.restore_irqen = &omap3xxx_prm_restore_irqen,
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};
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/*
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* omap3_prm_reset_src_map - map from bits in the PRM_RSTST hardware
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* register (which are specific to OMAP3xxx SoCs) to reset source ID
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* bit shifts (which is an OMAP SoC-independent enumeration)
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*/
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static struct prm_reset_src_map omap3xxx_prm_reset_src_map[] = {
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{ OMAP3430_GLOBAL_COLD_RST_SHIFT, OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
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{ OMAP3430_GLOBAL_SW_RST_SHIFT, OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
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{ OMAP3430_SECURITY_VIOL_RST_SHIFT, OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
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{ OMAP3430_MPU_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
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{ OMAP3430_SECURE_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
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{ OMAP3430_EXTERNAL_WARM_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
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{ OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT,
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OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT },
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{ OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT,
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OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT },
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{ OMAP3430_ICEPICK_RST_SHIFT, OMAP_ICEPICK_RST_SRC_ID_SHIFT },
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{ OMAP3430_ICECRUSHER_RST_SHIFT, OMAP_ICECRUSHER_RST_SRC_ID_SHIFT },
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{ -1, -1 },
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};
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/* PRM VP */
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/*
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* struct omap3_vp - OMAP3 VP register access description.
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* @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
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*/
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struct omap3_vp {
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u32 tranxdone_status;
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};
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static struct omap3_vp omap3_vp[] = {
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[OMAP3_VP_VDD_MPU_ID] = {
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.tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
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},
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[OMAP3_VP_VDD_CORE_ID] = {
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.tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
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},
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};
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#define MAX_VP_ID ARRAY_SIZE(omap3_vp);
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u32 omap3_prm_vp_check_txdone(u8 vp_id)
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{
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struct omap3_vp *vp = &omap3_vp[vp_id];
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u32 irqstatus;
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irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
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OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
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return irqstatus & vp->tranxdone_status;
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}
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void omap3_prm_vp_clear_txdone(u8 vp_id)
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{
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struct omap3_vp *vp = &omap3_vp[vp_id];
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omap2_prm_write_mod_reg(vp->tranxdone_status,
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OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
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}
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u32 omap3_prm_vcvp_read(u8 offset)
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{
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return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
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}
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void omap3_prm_vcvp_write(u32 val, u8 offset)
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{
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omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
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}
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u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
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{
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return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
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}
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/**
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* omap3xxx_prm_dpll3_reset - use DPLL3 reset to reboot the OMAP SoC
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*
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* Set the DPLL3 reset bit, which should reboot the SoC. This is the
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* recommended way to restart the SoC, considering Errata i520. No
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* return value.
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*/
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void omap3xxx_prm_dpll3_reset(void)
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{
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omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, OMAP3430_GR_MOD,
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OMAP2_RM_RSTCTRL);
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/* OCP barrier */
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omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP2_RM_RSTCTRL);
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}
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/**
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* omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
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* @events: ptr to a u32, preallocated by caller
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*
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* Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
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* MPU IRQs, and store the result into the u32 pointed to by @events.
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* No return value.
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*/
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void omap3xxx_prm_read_pending_irqs(unsigned long *events)
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{
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u32 mask, st;
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/* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
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mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
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st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
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events[0] = mask & st;
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}
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/**
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* omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
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*
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* Force any buffered writes to the PRM IP block to complete. Needed
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* by the PRM IRQ handler, which reads and writes directly to the IP
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* block, to avoid race conditions after acknowledging or clearing IRQ
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* bits. No return value.
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*/
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void omap3xxx_prm_ocp_barrier(void)
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{
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omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
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}
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/**
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* omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
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* @saved_mask: ptr to a u32 array to save IRQENABLE bits
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*
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* Save the PRM_IRQENABLE_MPU register to @saved_mask. @saved_mask
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* must be allocated by the caller. Intended to be used in the PRM
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* interrupt handler suspend callback. The OCP barrier is needed to
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* ensure the write to disable PRM interrupts reaches the PRM before
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* returning; otherwise, spurious interrupts might occur. No return
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* value.
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*/
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void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
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{
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saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
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OMAP3_PRM_IRQENABLE_MPU_OFFSET);
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omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
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/* OCP barrier */
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omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
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}
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/**
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* omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
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* @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
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*
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* Restore the PRM_IRQENABLE_MPU register from @saved_mask. Intended
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* to be used in the PRM interrupt handler resume callback to restore
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* values saved by omap3xxx_prm_save_and_clear_irqen(). No OCP
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* barrier should be needed here; any pending PRM interrupts will fire
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* once the writes reach the PRM. No return value.
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*/
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void omap3xxx_prm_restore_irqen(u32 *saved_mask)
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{
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omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
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OMAP3_PRM_IRQENABLE_MPU_OFFSET);
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}
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/**
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* omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
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*
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* Clear any previously-latched I/O wakeup events and ensure that the
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* I/O wakeup gates are aligned with the current mux settings. Works
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* by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
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* deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit. No
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* return value.
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*/
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void omap3xxx_prm_reconfigure_io_chain(void)
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{
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int i = 0;
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omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
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PM_WKEN);
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omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
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OMAP3430_ST_IO_CHAIN_MASK,
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MAX_IOPAD_LATCH_TIME, i);
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if (i == MAX_IOPAD_LATCH_TIME)
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pr_warn("PRM: I/O chain clock line assertion timed out\n");
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omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
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PM_WKEN);
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omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
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PM_WKST);
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omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
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}
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/**
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* omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
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*
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* Activates the I/O wakeup event latches and allows events logged by
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* those latches to signal a wakeup event to the PRCM. For I/O
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* wakeups to occur, WAKEUPENABLE bits must be set in the pad mux
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* registers, and omap3xxx_prm_reconfigure_io_chain() must be called.
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* No return value.
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*/
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static void __init omap3xxx_prm_enable_io_wakeup(void)
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{
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if (omap3_has_io_wakeup())
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omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
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PM_WKEN);
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}
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/**
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* omap3xxx_prm_read_reset_sources - return the last SoC reset source
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*
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* Return a u32 representing the last reset sources of the SoC. The
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* returned reset source bits are standardized across OMAP SoCs.
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*/
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static u32 omap3xxx_prm_read_reset_sources(void)
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{
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struct prm_reset_src_map *p;
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u32 r = 0;
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u32 v;
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v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST);
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p = omap3xxx_prm_reset_src_map;
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while (p->reg_shift >= 0 && p->std_shift >= 0) {
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if (v & (1 << p->reg_shift))
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r |= 1 << p->std_shift;
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p++;
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}
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return r;
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}
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/* Powerdomain low-level functions */
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/* Applicable only for OMAP3. Not supported on OMAP2 */
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static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
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{
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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OMAP3430_PM_PREPWSTST,
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OMAP3430_LASTPOWERSTATEENTERED_MASK);
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}
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static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
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{
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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OMAP2_PM_PWSTST,
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OMAP3430_LOGICSTATEST_MASK);
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}
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static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
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{
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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OMAP2_PM_PWSTCTRL,
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OMAP3430_LOGICSTATEST_MASK);
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}
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static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
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{
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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OMAP3430_PM_PREPWSTST,
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OMAP3430_LASTLOGICSTATEENTERED_MASK);
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}
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static int omap3_get_mem_bank_lastmemst_mask(u8 bank)
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{
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switch (bank) {
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case 0:
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return OMAP3430_LASTMEM1STATEENTERED_MASK;
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case 1:
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return OMAP3430_LASTMEM2STATEENTERED_MASK;
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case 2:
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return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK;
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case 3:
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return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK;
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default:
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WARN_ON(1); /* should never happen */
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return -EEXIST;
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}
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return 0;
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}
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static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
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{
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u32 m;
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m = omap3_get_mem_bank_lastmemst_mask(bank);
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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OMAP3430_PM_PREPWSTST, m);
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}
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static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
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{
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omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
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return 0;
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}
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static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
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{
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return omap2_prm_rmw_mod_reg_bits(0,
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1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
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pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
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}
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static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
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{
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return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
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0, pwrdm->prcm_offs,
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OMAP2_PM_PWSTCTRL);
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}
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struct pwrdm_ops omap3_pwrdm_operations = {
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.pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst,
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.pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst,
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.pwrdm_read_pwrst = omap2_pwrdm_read_pwrst,
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.pwrdm_read_prev_pwrst = omap3_pwrdm_read_prev_pwrst,
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.pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst,
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.pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst,
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.pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst,
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.pwrdm_read_prev_logic_pwrst = omap3_pwrdm_read_prev_logic_pwrst,
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.pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst,
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.pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst,
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.pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst,
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.pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst,
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.pwrdm_read_prev_mem_pwrst = omap3_pwrdm_read_prev_mem_pwrst,
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.pwrdm_clear_all_prev_pwrst = omap3_pwrdm_clear_all_prev_pwrst,
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.pwrdm_enable_hdwr_sar = omap3_pwrdm_enable_hdwr_sar,
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.pwrdm_disable_hdwr_sar = omap3_pwrdm_disable_hdwr_sar,
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.pwrdm_wait_transition = omap2_pwrdm_wait_transition,
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};
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/*
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*
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*/
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static struct prm_ll_data omap3xxx_prm_ll_data = {
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.read_reset_sources = &omap3xxx_prm_read_reset_sources,
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};
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int __init omap3xxx_prm_init(void)
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{
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if (!cpu_is_omap34xx())
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return 0;
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return prm_register(&omap3xxx_prm_ll_data);
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}
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static int __init omap3xxx_prm_late_init(void)
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{
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int ret;
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if (!cpu_is_omap34xx())
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return 0;
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omap3xxx_prm_enable_io_wakeup();
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ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
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if (!ret)
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irq_set_status_flags(omap_prcm_event_to_irq("io"),
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IRQ_NOAUTOEN);
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return ret;
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}
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subsys_initcall(omap3xxx_prm_late_init);
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static void __exit omap3xxx_prm_exit(void)
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{
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if (!cpu_is_omap34xx())
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return;
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/* Should never happen */
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WARN(prm_unregister(&omap3xxx_prm_ll_data),
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"%s: prm_ll_data function pointer mismatch\n", __func__);
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}
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__exitcall(omap3xxx_prm_exit);
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