forked from Minki/linux
146 lines
3.8 KiB
C
146 lines
3.8 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004, 06 by Ralf Baechle (ralf@linux-mips.org)
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/mv643xx.h>
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#include <linux/init.h>
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#include <asm/marvell.h>
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/*
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* We assume the address ranges have already been setup appropriately by
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* the firmware. PMON in case of the Ocelot C does that.
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*/
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static struct resource mv_pci_io_mem0_resource = {
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.name = "MV64340 PCI0 IO MEM",
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.flags = IORESOURCE_IO
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};
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static struct resource mv_pci_mem0_resource = {
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.name = "MV64340 PCI0 MEM",
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.flags = IORESOURCE_MEM
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};
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static struct mv_pci_controller mv_bus0_controller = {
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.pcic = {
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.pci_ops = &mv_pci_ops,
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.mem_resource = &mv_pci_mem0_resource,
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.io_resource = &mv_pci_io_mem0_resource,
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},
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.config_addr = MV64340_PCI_0_CONFIG_ADDR,
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.config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
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};
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static uint32_t mv_io_base, mv_io_size;
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static void mv64340_pci0_init(void)
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{
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uint32_t mem0_base, mem0_size;
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uint32_t io_base, io_size;
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io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16;
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io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16;
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mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16;
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mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16;
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mv_pci_io_mem0_resource.start = 0;
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mv_pci_io_mem0_resource.end = io_size - 1;
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mv_pci_mem0_resource.start = mem0_base;
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mv_pci_mem0_resource.end = mem0_base + mem0_size - 1;
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mv_bus0_controller.pcic.mem_offset = mem0_base;
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mv_bus0_controller.pcic.io_offset = 0;
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ioport_resource.end = io_size - 1;
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register_pci_controller(&mv_bus0_controller.pcic);
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mv_io_base = io_base;
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mv_io_size = io_size;
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}
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static struct resource mv_pci_io_mem1_resource = {
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.name = "MV64340 PCI1 IO MEM",
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.flags = IORESOURCE_IO
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};
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static struct resource mv_pci_mem1_resource = {
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.name = "MV64340 PCI1 MEM",
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.flags = IORESOURCE_MEM
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};
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static struct mv_pci_controller mv_bus1_controller = {
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.pcic = {
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.pci_ops = &mv_pci_ops,
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.mem_resource = &mv_pci_mem1_resource,
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.io_resource = &mv_pci_io_mem1_resource,
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},
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.config_addr = MV64340_PCI_1_CONFIG_ADDR,
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.config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
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};
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static __init void mv64340_pci1_init(void)
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{
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uint32_t mem0_base, mem0_size;
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uint32_t io_base, io_size;
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io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16;
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io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16;
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mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16;
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mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16;
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/*
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* Here we assume the I/O window of second bus to be contiguous with
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* the first. A gap is no problem but would waste address space for
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* remapping the port space.
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*/
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mv_pci_io_mem1_resource.start = mv_io_size;
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mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1;
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mv_pci_mem1_resource.start = mem0_base;
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mv_pci_mem1_resource.end = mem0_base + mem0_size - 1;
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mv_bus1_controller.pcic.mem_offset = mem0_base;
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mv_bus1_controller.pcic.io_offset = 0;
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ioport_resource.end = io_base + io_size -mv_io_base - 1;
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register_pci_controller(&mv_bus1_controller.pcic);
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mv_io_size = io_base + io_size - mv_io_base;
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}
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static __init int __init ocelot_c_pci_init(void)
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{
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unsigned long io_v_base;
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uint32_t enable;
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enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
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/*
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* We require at least one enabled I/O or PCI memory window or we
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* will ignore this PCI bus. We ignore PCI windows 1, 2 and 3.
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*/
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if (enable & (0x01 << 9) || enable & (0x01 << 10))
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mv64340_pci0_init();
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if (enable & (0x01 << 14) || enable & (0x01 << 15))
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mv64340_pci1_init();
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if (mv_io_size) {
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io_v_base = (unsigned long) ioremap(mv_io_base, mv_io_size);
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if (!io_v_base)
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panic("Could not ioremap I/O port range");
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set_io_port_base(io_v_base);
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}
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return 0;
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}
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arch_initcall(ocelot_c_pci_init);
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