forked from Minki/linux
3060e9f0d1
The ARM architecture defines the memory locations that are permitted
to be accessed as the result of a speculative instruction fetch from
an exception level for which all stages of translation are disabled.
Specifically, the core is permitted to speculatively fetch from the
4KB region containing the current program counter 4K and next 4K.
When translation is changed from enabled to disabled for the running
exception level (SCTLR_ELn[M] changed from a value of 1 to 0), the
Falkor core may errantly speculatively access memory locations outside
of the 4KB region permitted by the architecture. The errant memory
access may lead to one of the following unexpected behaviors.
1) A System Error Interrupt (SEI) being raised by the Falkor core due
to the errant memory access attempting to access a region of memory
that is protected by a slave-side memory protection unit.
2) Unpredictable device behavior due to a speculative read from device
memory. This behavior may only occur if the instruction cache is
disabled prior to or coincident with translation being changed from
enabled to disabled.
The conditions leading to this erratum will not occur when either of the
following occur:
1) A higher exception level disables translation of a lower exception level
(e.g. EL2 changing SCTLR_EL1[M] from a value of 1 to 0).
2) An exception level disabling its stage-1 translation if its stage-2
translation is enabled (e.g. EL1 changing SCTLR_EL1[M] from a value of 1
to 0 when HCR_EL2[VM] has a value of 1).
To avoid the errant behavior, software must execute an ISB immediately
prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0.
Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
537 lines
12 KiB
C
537 lines
12 KiB
C
/*
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* Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
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*
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* Copyright (C) 1996-2000 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASSEMBLY__
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#error "Only include this from assembly code"
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#endif
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#ifndef __ASM_ASSEMBLER_H
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#define __ASM_ASSEMBLER_H
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#include <asm/asm-offsets.h>
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#include <asm/cpufeature.h>
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#include <asm/debug-monitors.h>
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#include <asm/page.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/ptrace.h>
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#include <asm/thread_info.h>
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.macro save_and_disable_daif, flags
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mrs \flags, daif
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msr daifset, #0xf
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.endm
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.macro disable_daif
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msr daifset, #0xf
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.endm
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.macro enable_daif
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msr daifclr, #0xf
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.endm
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.macro restore_daif, flags:req
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msr daif, \flags
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.endm
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/* Only on aarch64 pstate, PSR_D_BIT is different for aarch32 */
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.macro inherit_daif, pstate:req, tmp:req
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and \tmp, \pstate, #(PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
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msr daif, \tmp
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.endm
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/* IRQ is the lowest priority flag, unconditionally unmask the rest. */
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.macro enable_da_f
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msr daifclr, #(8 | 4 | 1)
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.endm
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/*
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* Enable and disable interrupts.
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*/
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.macro disable_irq
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msr daifset, #2
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.endm
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.macro enable_irq
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msr daifclr, #2
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.endm
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.macro save_and_disable_irq, flags
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mrs \flags, daif
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msr daifset, #2
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.endm
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.macro restore_irq, flags
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msr daif, \flags
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.endm
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.macro enable_dbg
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msr daifclr, #8
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.endm
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.macro disable_step_tsk, flgs, tmp
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tbz \flgs, #TIF_SINGLESTEP, 9990f
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mrs \tmp, mdscr_el1
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bic \tmp, \tmp, #DBG_MDSCR_SS
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msr mdscr_el1, \tmp
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isb // Synchronise with enable_dbg
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9990:
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.endm
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/* call with daif masked */
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.macro enable_step_tsk, flgs, tmp
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tbz \flgs, #TIF_SINGLESTEP, 9990f
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mrs \tmp, mdscr_el1
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orr \tmp, \tmp, #DBG_MDSCR_SS
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msr mdscr_el1, \tmp
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9990:
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.endm
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/*
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* SMP data memory barrier
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*/
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.macro smp_dmb, opt
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dmb \opt
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.endm
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/*
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* RAS Error Synchronization barrier
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*/
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.macro esb
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hint #16
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.endm
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/*
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* NOP sequence
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*/
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.macro nops, num
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.rept \num
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nop
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.endr
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.endm
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/*
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* Emit an entry into the exception table
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*/
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.macro _asm_extable, from, to
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.pushsection __ex_table, "a"
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.align 3
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.long (\from - .), (\to - .)
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.popsection
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.endm
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#define USER(l, x...) \
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9999: x; \
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_asm_extable 9999b, l
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/*
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* Register aliases.
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*/
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lr .req x30 // link register
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/*
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* Vector entry
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*/
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.macro ventry label
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.align 7
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b \label
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.endm
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/*
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* Select code when configured for BE.
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*/
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#ifdef CONFIG_CPU_BIG_ENDIAN
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#define CPU_BE(code...) code
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#else
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#define CPU_BE(code...)
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#endif
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/*
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* Select code when configured for LE.
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*/
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#ifdef CONFIG_CPU_BIG_ENDIAN
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#define CPU_LE(code...)
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#else
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#define CPU_LE(code...) code
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#endif
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/*
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* Define a macro that constructs a 64-bit value by concatenating two
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* 32-bit registers. Note that on big endian systems the order of the
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* registers is swapped.
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*/
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#ifndef CONFIG_CPU_BIG_ENDIAN
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.macro regs_to_64, rd, lbits, hbits
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#else
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.macro regs_to_64, rd, hbits, lbits
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#endif
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orr \rd, \lbits, \hbits, lsl #32
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.endm
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/*
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* Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
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* <symbol> is within the range +/- 4 GB of the PC when running
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* in core kernel context. In module context, a movz/movk sequence
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* is used, since modules may be loaded far away from the kernel
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* when KASLR is in effect.
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*/
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/*
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* @dst: destination register (64 bit wide)
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* @sym: name of the symbol
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*/
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.macro adr_l, dst, sym
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#ifndef MODULE
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adrp \dst, \sym
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add \dst, \dst, :lo12:\sym
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#else
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movz \dst, #:abs_g3:\sym
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movk \dst, #:abs_g2_nc:\sym
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movk \dst, #:abs_g1_nc:\sym
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movk \dst, #:abs_g0_nc:\sym
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#endif
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.endm
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/*
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* @dst: destination register (32 or 64 bit wide)
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* @sym: name of the symbol
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* @tmp: optional 64-bit scratch register to be used if <dst> is a
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* 32-bit wide register, in which case it cannot be used to hold
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* the address
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*/
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.macro ldr_l, dst, sym, tmp=
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#ifndef MODULE
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.ifb \tmp
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adrp \dst, \sym
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ldr \dst, [\dst, :lo12:\sym]
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.else
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adrp \tmp, \sym
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ldr \dst, [\tmp, :lo12:\sym]
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.endif
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#else
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.ifb \tmp
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adr_l \dst, \sym
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ldr \dst, [\dst]
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.else
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adr_l \tmp, \sym
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ldr \dst, [\tmp]
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.endif
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#endif
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.endm
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/*
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* @src: source register (32 or 64 bit wide)
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* @sym: name of the symbol
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* @tmp: mandatory 64-bit scratch register to calculate the address
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* while <src> needs to be preserved.
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*/
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.macro str_l, src, sym, tmp
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#ifndef MODULE
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adrp \tmp, \sym
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str \src, [\tmp, :lo12:\sym]
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#else
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adr_l \tmp, \sym
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str \src, [\tmp]
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#endif
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.endm
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/*
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* @dst: Result of per_cpu(sym, smp_processor_id()), can be SP for
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* non-module code
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* @sym: The name of the per-cpu variable
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* @tmp: scratch register
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*/
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.macro adr_this_cpu, dst, sym, tmp
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#ifndef MODULE
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adrp \tmp, \sym
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add \dst, \tmp, #:lo12:\sym
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#else
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adr_l \dst, \sym
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#endif
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alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
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mrs \tmp, tpidr_el1
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alternative_else
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mrs \tmp, tpidr_el2
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alternative_endif
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add \dst, \dst, \tmp
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.endm
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/*
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* @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id()))
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* @sym: The name of the per-cpu variable
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* @tmp: scratch register
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*/
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.macro ldr_this_cpu dst, sym, tmp
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adr_l \dst, \sym
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alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
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mrs \tmp, tpidr_el1
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alternative_else
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mrs \tmp, tpidr_el2
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alternative_endif
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ldr \dst, [\dst, \tmp]
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.endm
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/*
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* vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
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*/
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.macro vma_vm_mm, rd, rn
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ldr \rd, [\rn, #VMA_VM_MM]
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.endm
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/*
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* mmid - get context id from mm pointer (mm->context.id)
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*/
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.macro mmid, rd, rn
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ldr \rd, [\rn, #MM_CONTEXT_ID]
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.endm
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/*
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* read_ctr - read CTR_EL0. If the system has mismatched
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* cache line sizes, provide the system wide safe value
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* from arm64_ftr_reg_ctrel0.sys_val
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*/
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.macro read_ctr, reg
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alternative_if_not ARM64_MISMATCHED_CACHE_LINE_SIZE
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mrs \reg, ctr_el0 // read CTR
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nop
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alternative_else
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ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL
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alternative_endif
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.endm
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/*
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* raw_dcache_line_size - get the minimum D-cache line size on this CPU
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* from the CTR register.
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*/
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.macro raw_dcache_line_size, reg, tmp
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mrs \tmp, ctr_el0 // read CTR
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ubfm \tmp, \tmp, #16, #19 // cache line size encoding
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mov \reg, #4 // bytes per word
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lsl \reg, \reg, \tmp // actual cache line size
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.endm
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/*
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* dcache_line_size - get the safe D-cache line size across all CPUs
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*/
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.macro dcache_line_size, reg, tmp
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read_ctr \tmp
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ubfm \tmp, \tmp, #16, #19 // cache line size encoding
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mov \reg, #4 // bytes per word
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lsl \reg, \reg, \tmp // actual cache line size
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.endm
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/*
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* raw_icache_line_size - get the minimum I-cache line size on this CPU
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* from the CTR register.
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*/
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.macro raw_icache_line_size, reg, tmp
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mrs \tmp, ctr_el0 // read CTR
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and \tmp, \tmp, #0xf // cache line size encoding
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mov \reg, #4 // bytes per word
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lsl \reg, \reg, \tmp // actual cache line size
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.endm
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/*
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* icache_line_size - get the safe I-cache line size across all CPUs
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*/
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.macro icache_line_size, reg, tmp
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read_ctr \tmp
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and \tmp, \tmp, #0xf // cache line size encoding
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mov \reg, #4 // bytes per word
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lsl \reg, \reg, \tmp // actual cache line size
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.endm
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/*
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* tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map
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*/
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.macro tcr_set_idmap_t0sz, valreg, tmpreg
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ldr_l \tmpreg, idmap_t0sz
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bfi \valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
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.endm
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/*
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* tcr_compute_pa_size - set TCR.(I)PS to the highest supported
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* ID_AA64MMFR0_EL1.PARange value
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*
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* tcr: register with the TCR_ELx value to be updated
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* pos: IPS or PS bitfield position
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* tmp{0,1}: temporary registers
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*/
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.macro tcr_compute_pa_size, tcr, pos, tmp0, tmp1
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mrs \tmp0, ID_AA64MMFR0_EL1
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// Narrow PARange to fit the PS field in TCR_ELx
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ubfx \tmp0, \tmp0, #ID_AA64MMFR0_PARANGE_SHIFT, #3
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mov \tmp1, #ID_AA64MMFR0_PARANGE_MAX
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cmp \tmp0, \tmp1
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csel \tmp0, \tmp1, \tmp0, hi
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bfi \tcr, \tmp0, \pos, #3
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.endm
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/*
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* Macro to perform a data cache maintenance for the interval
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* [kaddr, kaddr + size)
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*
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* op: operation passed to dc instruction
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* domain: domain used in dsb instruciton
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* kaddr: starting virtual address of the region
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* size: size of the region
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* Corrupts: kaddr, size, tmp1, tmp2
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*/
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.macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2
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dcache_line_size \tmp1, \tmp2
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add \size, \kaddr, \size
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sub \tmp2, \tmp1, #1
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bic \kaddr, \kaddr, \tmp2
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9998:
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.if (\op == cvau || \op == cvac)
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alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE
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dc \op, \kaddr
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alternative_else
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dc civac, \kaddr
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alternative_endif
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.elseif (\op == cvap)
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alternative_if ARM64_HAS_DCPOP
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sys 3, c7, c12, 1, \kaddr // dc cvap
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alternative_else
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dc cvac, \kaddr
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alternative_endif
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.else
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dc \op, \kaddr
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.endif
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add \kaddr, \kaddr, \tmp1
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cmp \kaddr, \size
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b.lo 9998b
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dsb \domain
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.endm
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/*
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* reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
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*/
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.macro reset_pmuserenr_el0, tmpreg
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mrs \tmpreg, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
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sbfx \tmpreg, \tmpreg, #8, #4
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cmp \tmpreg, #1 // Skip if no PMU present
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b.lt 9000f
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msr pmuserenr_el0, xzr // Disable PMU access from EL0
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9000:
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.endm
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/*
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* copy_page - copy src to dest using temp registers t1-t8
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*/
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.macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req
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9998: ldp \t1, \t2, [\src]
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ldp \t3, \t4, [\src, #16]
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ldp \t5, \t6, [\src, #32]
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ldp \t7, \t8, [\src, #48]
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add \src, \src, #64
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stnp \t1, \t2, [\dest]
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stnp \t3, \t4, [\dest, #16]
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stnp \t5, \t6, [\dest, #32]
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stnp \t7, \t8, [\dest, #48]
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add \dest, \dest, #64
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tst \src, #(PAGE_SIZE - 1)
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b.ne 9998b
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.endm
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/*
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* Annotate a function as position independent, i.e., safe to be called before
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* the kernel virtual mapping is activated.
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*/
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#define ENDPIPROC(x) \
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.globl __pi_##x; \
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.type __pi_##x, %function; \
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.set __pi_##x, x; \
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.size __pi_##x, . - x; \
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ENDPROC(x)
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/*
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* Annotate a function as being unsuitable for kprobes.
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*/
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#ifdef CONFIG_KPROBES
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#define NOKPROBE(x) \
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.pushsection "_kprobe_blacklist", "aw"; \
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.quad x; \
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.popsection;
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#else
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#define NOKPROBE(x)
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#endif
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/*
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* Emit a 64-bit absolute little endian symbol reference in a way that
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* ensures that it will be resolved at build time, even when building a
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* PIE binary. This requires cooperation from the linker script, which
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* must emit the lo32/hi32 halves individually.
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*/
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.macro le64sym, sym
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.long \sym\()_lo32
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.long \sym\()_hi32
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.endm
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/*
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* mov_q - move an immediate constant into a 64-bit register using
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* between 2 and 4 movz/movk instructions (depending on the
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* magnitude and sign of the operand)
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*/
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.macro mov_q, reg, val
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.if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
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movz \reg, :abs_g1_s:\val
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.else
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.if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
|
|
movz \reg, :abs_g2_s:\val
|
|
.else
|
|
movz \reg, :abs_g3:\val
|
|
movk \reg, :abs_g2_nc:\val
|
|
.endif
|
|
movk \reg, :abs_g1_nc:\val
|
|
.endif
|
|
movk \reg, :abs_g0_nc:\val
|
|
.endm
|
|
|
|
/*
|
|
* Return the current thread_info.
|
|
*/
|
|
.macro get_thread_info, rd
|
|
mrs \rd, sp_el0
|
|
.endm
|
|
|
|
/*
|
|
* Arrange a physical address in a TTBR register, taking care of 52-bit
|
|
* addresses.
|
|
*
|
|
* phys: physical address, preserved
|
|
* ttbr: returns the TTBR value
|
|
*/
|
|
.macro phys_to_ttbr, phys, ttbr
|
|
#ifdef CONFIG_ARM64_PA_BITS_52
|
|
orr \ttbr, \phys, \phys, lsr #46
|
|
and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
|
|
#else
|
|
mov \ttbr, \phys
|
|
#endif
|
|
.endm
|
|
|
|
/**
|
|
* Errata workaround prior to disable MMU. Insert an ISB immediately prior
|
|
* to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
|
|
*/
|
|
.macro pre_disable_mmu_workaround
|
|
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041
|
|
isb
|
|
#endif
|
|
.endm
|
|
|
|
#endif /* __ASM_ASSEMBLER_H */
|