forked from Minki/linux
2f4b829c62
The ARMv8.1 architecture extensions introduce support for hardware updates of the access and dirty information in page table entries. With TCR_EL1.HA enabled, when the CPU accesses an address with the PTE_AF bit cleared in the page table, instead of raising an access flag fault the CPU sets the actual page table entry bit. To ensure that kernel modifications to the page tables do not inadvertently revert a change introduced by hardware updates, the exclusive monitor (ldxr/stxr) is adopted in the pte accessors. When TCR_EL1.HD is enabled, a write access to a memory location with the DBM (Dirty Bit Management) bit set in the corresponding pte automatically clears the read-only bit (AP[2]). Such DBM bit maps onto the Linux PTE_WRITE bit and to check whether a writable (DBM set) page is dirty, the kernel tests the PTE_RDONLY bit. In order to allow read-only and dirty pages, the kernel needs to preserve the software dirty bit. The hardware dirty status is transferred to the software dirty bit in ptep_set_wrprotect() (using load/store exclusive loop) and pte_modify(). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> |
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| .. | ||
| cache.S | ||
| context.c | ||
| copypage.c | ||
| dma-mapping.c | ||
| dump.c | ||
| extable.c | ||
| fault.c | ||
| flush.c | ||
| hugetlbpage.c | ||
| init.c | ||
| ioremap.c | ||
| Makefile | ||
| mm.h | ||
| mmap.c | ||
| mmu.c | ||
| pageattr.c | ||
| pgd.c | ||
| proc-macros.S | ||
| proc.S | ||