forked from Minki/linux
1e6bb81c23
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: efc945fb72
("iio: adc: add support for ADC0831/ADC0832/ADC0834/ADC0838 chips")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Akinobu Mita <akinobu.mita@gmail.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-29-jic23@kernel.org
339 lines
8.0 KiB
C
339 lines
8.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* ADC0831/ADC0832/ADC0834/ADC0838 8-bit ADC driver
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*
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* Copyright (c) 2016 Akinobu Mita <akinobu.mita@gmail.com>
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*
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* Datasheet: https://www.ti.com/lit/ds/symlink/adc0832-n.pdf
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*/
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/spi/spi.h>
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#include <linux/iio/iio.h>
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#include <linux/regulator/consumer.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/trigger.h>
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#include <linux/iio/triggered_buffer.h>
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#include <linux/iio/trigger_consumer.h>
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enum {
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adc0831,
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adc0832,
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adc0834,
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adc0838,
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};
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struct adc0832 {
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struct spi_device *spi;
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struct regulator *reg;
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struct mutex lock;
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u8 mux_bits;
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/*
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* Max size needed: 16x 1 byte ADC data + 8 bytes timestamp
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* May be shorter if not all channels are enabled subject
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* to the timestamp remaining 8 byte aligned.
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*/
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u8 data[24] __aligned(8);
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u8 tx_buf[2] __aligned(IIO_DMA_MINALIGN);
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u8 rx_buf[2];
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};
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#define ADC0832_VOLTAGE_CHANNEL(chan) \
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{ \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = chan, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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.scan_index = chan, \
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.scan_type = { \
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.sign = 'u', \
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.realbits = 8, \
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.storagebits = 8, \
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}, \
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}
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#define ADC0832_VOLTAGE_CHANNEL_DIFF(chan1, chan2, si) \
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{ \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = (chan1), \
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.channel2 = (chan2), \
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.differential = 1, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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.scan_index = si, \
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.scan_type = { \
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.sign = 'u', \
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.realbits = 8, \
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.storagebits = 8, \
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}, \
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}
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static const struct iio_chan_spec adc0831_channels[] = {
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ADC0832_VOLTAGE_CHANNEL_DIFF(0, 1, 0),
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IIO_CHAN_SOFT_TIMESTAMP(1),
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};
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static const struct iio_chan_spec adc0832_channels[] = {
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ADC0832_VOLTAGE_CHANNEL(0),
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ADC0832_VOLTAGE_CHANNEL(1),
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ADC0832_VOLTAGE_CHANNEL_DIFF(0, 1, 2),
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ADC0832_VOLTAGE_CHANNEL_DIFF(1, 0, 3),
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IIO_CHAN_SOFT_TIMESTAMP(4),
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};
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static const struct iio_chan_spec adc0834_channels[] = {
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ADC0832_VOLTAGE_CHANNEL(0),
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ADC0832_VOLTAGE_CHANNEL(1),
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ADC0832_VOLTAGE_CHANNEL(2),
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ADC0832_VOLTAGE_CHANNEL(3),
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ADC0832_VOLTAGE_CHANNEL_DIFF(0, 1, 4),
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ADC0832_VOLTAGE_CHANNEL_DIFF(1, 0, 5),
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ADC0832_VOLTAGE_CHANNEL_DIFF(2, 3, 6),
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ADC0832_VOLTAGE_CHANNEL_DIFF(3, 2, 7),
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IIO_CHAN_SOFT_TIMESTAMP(8),
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};
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static const struct iio_chan_spec adc0838_channels[] = {
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ADC0832_VOLTAGE_CHANNEL(0),
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ADC0832_VOLTAGE_CHANNEL(1),
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ADC0832_VOLTAGE_CHANNEL(2),
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ADC0832_VOLTAGE_CHANNEL(3),
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ADC0832_VOLTAGE_CHANNEL(4),
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ADC0832_VOLTAGE_CHANNEL(5),
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ADC0832_VOLTAGE_CHANNEL(6),
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ADC0832_VOLTAGE_CHANNEL(7),
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ADC0832_VOLTAGE_CHANNEL_DIFF(0, 1, 8),
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ADC0832_VOLTAGE_CHANNEL_DIFF(1, 0, 9),
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ADC0832_VOLTAGE_CHANNEL_DIFF(2, 3, 10),
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ADC0832_VOLTAGE_CHANNEL_DIFF(3, 2, 11),
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ADC0832_VOLTAGE_CHANNEL_DIFF(4, 5, 12),
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ADC0832_VOLTAGE_CHANNEL_DIFF(5, 4, 13),
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ADC0832_VOLTAGE_CHANNEL_DIFF(6, 7, 14),
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ADC0832_VOLTAGE_CHANNEL_DIFF(7, 6, 15),
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IIO_CHAN_SOFT_TIMESTAMP(16),
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};
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static int adc0831_adc_conversion(struct adc0832 *adc)
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{
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struct spi_device *spi = adc->spi;
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int ret;
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ret = spi_read(spi, &adc->rx_buf, 2);
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if (ret)
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return ret;
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/*
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* Skip TRI-STATE and a leading zero
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*/
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return (adc->rx_buf[0] << 2 & 0xff) | (adc->rx_buf[1] >> 6);
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}
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static int adc0832_adc_conversion(struct adc0832 *adc, int channel,
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bool differential)
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{
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struct spi_device *spi = adc->spi;
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struct spi_transfer xfer = {
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.tx_buf = adc->tx_buf,
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.rx_buf = adc->rx_buf,
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.len = 2,
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};
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int ret;
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if (!adc->mux_bits)
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return adc0831_adc_conversion(adc);
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/* start bit */
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adc->tx_buf[0] = 1 << (adc->mux_bits + 1);
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/* single-ended or differential */
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adc->tx_buf[0] |= differential ? 0 : (1 << adc->mux_bits);
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/* odd / sign */
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adc->tx_buf[0] |= (channel % 2) << (adc->mux_bits - 1);
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/* select */
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if (adc->mux_bits > 1)
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adc->tx_buf[0] |= channel / 2;
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/* align Data output BIT7 (MSB) to 8-bit boundary */
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adc->tx_buf[0] <<= 1;
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ret = spi_sync_transfer(spi, &xfer, 1);
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if (ret)
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return ret;
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return adc->rx_buf[1];
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}
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static int adc0832_read_raw(struct iio_dev *iio,
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struct iio_chan_spec const *channel, int *value,
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int *shift, long mask)
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{
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struct adc0832 *adc = iio_priv(iio);
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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mutex_lock(&adc->lock);
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*value = adc0832_adc_conversion(adc, channel->channel,
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channel->differential);
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mutex_unlock(&adc->lock);
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if (*value < 0)
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return *value;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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*value = regulator_get_voltage(adc->reg);
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if (*value < 0)
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return *value;
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/* convert regulator output voltage to mV */
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*value /= 1000;
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*shift = 8;
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return IIO_VAL_FRACTIONAL_LOG2;
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}
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return -EINVAL;
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}
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static const struct iio_info adc0832_info = {
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.read_raw = adc0832_read_raw,
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};
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static irqreturn_t adc0832_trigger_handler(int irq, void *p)
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{
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struct iio_poll_func *pf = p;
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struct iio_dev *indio_dev = pf->indio_dev;
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struct adc0832 *adc = iio_priv(indio_dev);
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int scan_index;
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int i = 0;
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mutex_lock(&adc->lock);
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for_each_set_bit(scan_index, indio_dev->active_scan_mask,
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indio_dev->masklength) {
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const struct iio_chan_spec *scan_chan =
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&indio_dev->channels[scan_index];
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int ret = adc0832_adc_conversion(adc, scan_chan->channel,
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scan_chan->differential);
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if (ret < 0) {
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dev_warn(&adc->spi->dev,
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"failed to get conversion data\n");
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goto out;
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}
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adc->data[i] = ret;
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i++;
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}
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iio_push_to_buffers_with_timestamp(indio_dev, adc->data,
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iio_get_time_ns(indio_dev));
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out:
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mutex_unlock(&adc->lock);
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iio_trigger_notify_done(indio_dev->trig);
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return IRQ_HANDLED;
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}
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static void adc0832_reg_disable(void *reg)
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{
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regulator_disable(reg);
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}
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static int adc0832_probe(struct spi_device *spi)
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{
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struct iio_dev *indio_dev;
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struct adc0832 *adc;
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int ret;
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indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
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if (!indio_dev)
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return -ENOMEM;
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adc = iio_priv(indio_dev);
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adc->spi = spi;
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mutex_init(&adc->lock);
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indio_dev->name = spi_get_device_id(spi)->name;
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indio_dev->info = &adc0832_info;
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indio_dev->modes = INDIO_DIRECT_MODE;
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switch (spi_get_device_id(spi)->driver_data) {
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case adc0831:
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adc->mux_bits = 0;
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indio_dev->channels = adc0831_channels;
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indio_dev->num_channels = ARRAY_SIZE(adc0831_channels);
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break;
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case adc0832:
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adc->mux_bits = 1;
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indio_dev->channels = adc0832_channels;
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indio_dev->num_channels = ARRAY_SIZE(adc0832_channels);
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break;
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case adc0834:
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adc->mux_bits = 2;
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indio_dev->channels = adc0834_channels;
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indio_dev->num_channels = ARRAY_SIZE(adc0834_channels);
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break;
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case adc0838:
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adc->mux_bits = 3;
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indio_dev->channels = adc0838_channels;
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indio_dev->num_channels = ARRAY_SIZE(adc0838_channels);
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break;
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default:
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return -EINVAL;
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}
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adc->reg = devm_regulator_get(&spi->dev, "vref");
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if (IS_ERR(adc->reg))
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return PTR_ERR(adc->reg);
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ret = regulator_enable(adc->reg);
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if (ret)
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return ret;
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ret = devm_add_action_or_reset(&spi->dev, adc0832_reg_disable,
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adc->reg);
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if (ret)
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return ret;
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ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
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adc0832_trigger_handler, NULL);
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if (ret)
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return ret;
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return devm_iio_device_register(&spi->dev, indio_dev);
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}
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static const struct of_device_id adc0832_dt_ids[] = {
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{ .compatible = "ti,adc0831", },
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{ .compatible = "ti,adc0832", },
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{ .compatible = "ti,adc0834", },
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{ .compatible = "ti,adc0838", },
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{}
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};
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MODULE_DEVICE_TABLE(of, adc0832_dt_ids);
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static const struct spi_device_id adc0832_id[] = {
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{ "adc0831", adc0831 },
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{ "adc0832", adc0832 },
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{ "adc0834", adc0834 },
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{ "adc0838", adc0838 },
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{}
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};
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MODULE_DEVICE_TABLE(spi, adc0832_id);
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static struct spi_driver adc0832_driver = {
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.driver = {
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.name = "adc0832",
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.of_match_table = adc0832_dt_ids,
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},
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.probe = adc0832_probe,
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.id_table = adc0832_id,
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};
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module_spi_driver(adc0832_driver);
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MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>");
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MODULE_DESCRIPTION("ADC0831/ADC0832/ADC0834/ADC0838 driver");
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MODULE_LICENSE("GPL v2");
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