forked from Minki/linux
2eb5618de8
for USP-based UART, we use two gpios as RTS and CST pins. Signed-off-by: Qipan Li <Qipan.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
1062 lines
32 KiB
C
1062 lines
32 KiB
C
/*
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* Driver for CSR SiRFprimaII onboard UARTs.
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/sysrq.h>
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#include <linux/console.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/serial_core.h>
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#include <linux/serial.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/of_gpio.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include "sirfsoc_uart.h"
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static unsigned int
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sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count);
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static unsigned int
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sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count);
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static struct uart_driver sirfsoc_uart_drv;
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static const struct sirfsoc_baudrate_to_regv baudrate_to_regv[] = {
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{4000000, 2359296},
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{3500000, 1310721},
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{3000000, 1572865},
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{2500000, 1245186},
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{2000000, 1572866},
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{1500000, 1245188},
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{1152000, 1638404},
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{1000000, 1572869},
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{921600, 1114120},
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{576000, 1245196},
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{500000, 1245198},
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{460800, 1572876},
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{230400, 1310750},
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{115200, 1310781},
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{57600, 1310843},
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{38400, 1114328},
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{19200, 1114545},
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{9600, 1114979},
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};
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static struct sirfsoc_uart_port sirfsoc_uart_ports[SIRFSOC_UART_NR] = {
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[0] = {
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.port = {
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF,
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.line = 0,
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},
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},
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[1] = {
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.port = {
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF,
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.line = 1,
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},
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},
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[2] = {
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.port = {
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF,
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.line = 2,
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},
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},
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[3] = {
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.port = {
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF,
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.line = 3,
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},
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},
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[4] = {
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.port = {
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF,
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.line = 4,
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},
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},
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};
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static inline struct sirfsoc_uart_port *to_sirfport(struct uart_port *port)
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{
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return container_of(port, struct sirfsoc_uart_port, port);
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}
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static inline unsigned int sirfsoc_uart_tx_empty(struct uart_port *port)
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{
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unsigned long reg;
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struct sirfsoc_uart_port *sirfport = to_sirfport(port);
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struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
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struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
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reg = rd_regl(port, ureg->sirfsoc_tx_fifo_status);
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return (reg & ufifo_st->ff_empty(port->line)) ? TIOCSER_TEMT : 0;
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}
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static unsigned int sirfsoc_uart_get_mctrl(struct uart_port *port)
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{
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struct sirfsoc_uart_port *sirfport = to_sirfport(port);
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struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
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if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled)
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goto cts_asserted;
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if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
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if (!(rd_regl(port, ureg->sirfsoc_afc_ctrl) &
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SIRFUART_AFC_CTS_STATUS))
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goto cts_asserted;
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else
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goto cts_deasserted;
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} else {
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if (!gpio_get_value(sirfport->cts_gpio))
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goto cts_asserted;
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else
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goto cts_deasserted;
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}
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cts_deasserted:
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return TIOCM_CAR | TIOCM_DSR;
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cts_asserted:
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return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
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}
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static void sirfsoc_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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struct sirfsoc_uart_port *sirfport = to_sirfport(port);
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struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
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unsigned int assert = mctrl & TIOCM_RTS;
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unsigned int val = assert ? SIRFUART_AFC_CTRL_RX_THD : 0x0;
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unsigned int current_val;
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if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled)
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return;
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if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
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current_val = rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0xFF;
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val |= current_val;
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wr_regl(port, ureg->sirfsoc_afc_ctrl, val);
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} else {
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if (!val)
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gpio_set_value(sirfport->rts_gpio, 1);
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else
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gpio_set_value(sirfport->rts_gpio, 0);
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}
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}
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static void sirfsoc_uart_stop_tx(struct uart_port *port)
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{
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struct sirfsoc_uart_port *sirfport = to_sirfport(port);
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struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
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struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
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unsigned int regv;
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if (!sirfport->is_marco) {
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regv = rd_regl(port, ureg->sirfsoc_int_en_reg);
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wr_regl(port, ureg->sirfsoc_int_en_reg,
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regv & ~uint_en->sirfsoc_txfifo_empty_en);
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} else
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wr_regl(port, SIRFUART_INT_EN_CLR,
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uint_en->sirfsoc_txfifo_empty_en);
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}
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static void sirfsoc_uart_start_tx(struct uart_port *port)
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{
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struct sirfsoc_uart_port *sirfport = to_sirfport(port);
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struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
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struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
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unsigned long regv;
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sirfsoc_uart_pio_tx_chars(sirfport, 1);
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wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
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if (!sirfport->is_marco) {
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regv = rd_regl(port, ureg->sirfsoc_int_en_reg);
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wr_regl(port, ureg->sirfsoc_int_en_reg, regv |
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uint_en->sirfsoc_txfifo_empty_en);
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} else
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wr_regl(port, ureg->sirfsoc_int_en_reg,
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uint_en->sirfsoc_txfifo_empty_en);
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}
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static void sirfsoc_uart_stop_rx(struct uart_port *port)
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{
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struct sirfsoc_uart_port *sirfport = to_sirfport(port);
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struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
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struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
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unsigned long reg;
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wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
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if (!sirfport->is_marco) {
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reg = rd_regl(port, ureg->sirfsoc_int_en_reg);
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wr_regl(port, ureg->sirfsoc_int_en_reg,
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reg & ~(SIRFUART_RX_IO_INT_EN(port, uint_en)));
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} else
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wr_regl(port, SIRFUART_INT_EN_CLR,
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SIRFUART_RX_IO_INT_EN(port, uint_en));
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}
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static void sirfsoc_uart_disable_ms(struct uart_port *port)
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{
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struct sirfsoc_uart_port *sirfport = to_sirfport(port);
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struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
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struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
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if (!sirfport->hw_flow_ctrl)
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return;
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sirfport->ms_enabled = false;
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if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
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wr_regl(port, ureg->sirfsoc_afc_ctrl,
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rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0x3FF);
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if (!sirfport->is_marco)
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wr_regl(port, ureg->sirfsoc_int_en_reg,
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rd_regl(port, ureg->sirfsoc_int_en_reg)&
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~uint_en->sirfsoc_cts_en);
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else
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wr_regl(port, SIRFUART_INT_EN_CLR,
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uint_en->sirfsoc_cts_en);
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} else
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disable_irq(gpio_to_irq(sirfport->cts_gpio));
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}
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static irqreturn_t sirfsoc_uart_usp_cts_handler(int irq, void *dev_id)
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{
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struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
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struct uart_port *port = &sirfport->port;
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if (gpio_is_valid(sirfport->cts_gpio) && sirfport->ms_enabled)
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uart_handle_cts_change(port,
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!gpio_get_value(sirfport->cts_gpio));
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return IRQ_HANDLED;
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}
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static void sirfsoc_uart_enable_ms(struct uart_port *port)
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{
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struct sirfsoc_uart_port *sirfport = to_sirfport(port);
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struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
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struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
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if (!sirfport->hw_flow_ctrl)
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return;
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sirfport->ms_enabled = true;
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if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
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wr_regl(port, ureg->sirfsoc_afc_ctrl,
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rd_regl(port, ureg->sirfsoc_afc_ctrl) |
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SIRFUART_AFC_TX_EN | SIRFUART_AFC_RX_EN);
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if (!sirfport->is_marco)
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wr_regl(port, ureg->sirfsoc_int_en_reg,
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rd_regl(port, ureg->sirfsoc_int_en_reg)
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| uint_en->sirfsoc_cts_en);
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else
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wr_regl(port, ureg->sirfsoc_int_en_reg,
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uint_en->sirfsoc_cts_en);
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} else
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enable_irq(gpio_to_irq(sirfport->cts_gpio));
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}
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static void sirfsoc_uart_break_ctl(struct uart_port *port, int break_state)
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{
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struct sirfsoc_uart_port *sirfport = to_sirfport(port);
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struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
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if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
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unsigned long ulcon = rd_regl(port, ureg->sirfsoc_line_ctrl);
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if (break_state)
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ulcon |= SIRFUART_SET_BREAK;
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else
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ulcon &= ~SIRFUART_SET_BREAK;
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wr_regl(port, ureg->sirfsoc_line_ctrl, ulcon);
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}
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}
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static unsigned int
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sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count)
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{
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struct sirfsoc_uart_port *sirfport = to_sirfport(port);
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struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
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struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
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unsigned int ch, rx_count = 0;
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struct tty_struct *tty;
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tty = tty_port_tty_get(&port->state->port);
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if (!tty)
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return -ENODEV;
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while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) &
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ufifo_st->ff_empty(port->line))) {
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ch = rd_regl(port, ureg->sirfsoc_rx_fifo_data) |
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SIRFUART_DUMMY_READ;
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if (unlikely(uart_handle_sysrq_char(port, ch)))
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continue;
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uart_insert_char(port, 0, 0, ch, TTY_NORMAL);
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rx_count++;
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if (rx_count >= max_rx_count)
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break;
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}
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port->icount.rx += rx_count;
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tty_flip_buffer_push(&port->state->port);
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return rx_count;
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}
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static unsigned int
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sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count)
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{
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struct uart_port *port = &sirfport->port;
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struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
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struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
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struct circ_buf *xmit = &port->state->xmit;
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unsigned int num_tx = 0;
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while (!uart_circ_empty(xmit) &&
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!(rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
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ufifo_st->ff_full(port->line)) &&
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count--) {
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wr_regl(port, ureg->sirfsoc_tx_fifo_data,
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xmit->buf[xmit->tail]);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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num_tx++;
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}
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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return num_tx;
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}
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static irqreturn_t sirfsoc_uart_isr(int irq, void *dev_id)
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{
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unsigned long intr_status;
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unsigned long cts_status;
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unsigned long flag = TTY_NORMAL;
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struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
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struct uart_port *port = &sirfport->port;
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struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
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struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
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struct sirfsoc_int_status *uint_st = &sirfport->uart_reg->uart_int_st;
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struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
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struct uart_state *state = port->state;
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struct circ_buf *xmit = &port->state->xmit;
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spin_lock(&port->lock);
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intr_status = rd_regl(port, ureg->sirfsoc_int_st_reg);
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wr_regl(port, ureg->sirfsoc_int_st_reg, intr_status);
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if (unlikely(intr_status & (SIRFUART_ERR_INT_STAT(port, uint_st)))) {
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if (intr_status & uint_st->sirfsoc_rxd_brk) {
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port->icount.brk++;
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if (uart_handle_break(port))
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goto recv_char;
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}
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if (intr_status & uint_st->sirfsoc_rx_oflow)
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port->icount.overrun++;
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if (intr_status & uint_st->sirfsoc_frm_err) {
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port->icount.frame++;
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flag = TTY_FRAME;
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}
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if (intr_status & uint_st->sirfsoc_parity_err)
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flag = TTY_PARITY;
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wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
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wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
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wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START);
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intr_status &= port->read_status_mask;
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uart_insert_char(port, intr_status,
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uint_en->sirfsoc_rx_oflow_en, 0, flag);
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tty_flip_buffer_push(&state->port);
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}
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recv_char:
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if ((sirfport->uart_reg->uart_type == SIRF_REAL_UART) &&
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(intr_status & SIRFUART_CTS_INT_ST(uint_st))) {
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cts_status = rd_regl(port, ureg->sirfsoc_afc_ctrl) &
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SIRFUART_AFC_CTS_STATUS;
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if (cts_status != 0)
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cts_status = 0;
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else
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cts_status = 1;
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uart_handle_cts_change(port, cts_status);
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wake_up_interruptible(&state->port.delta_msr_wait);
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}
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if (intr_status & SIRFUART_RX_IO_INT_ST(uint_st))
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sirfsoc_uart_pio_rx_chars(port, SIRFSOC_UART_IO_RX_MAX_CNT);
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if (intr_status & uint_st->sirfsoc_txfifo_empty) {
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if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
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spin_unlock(&port->lock);
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return IRQ_HANDLED;
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} else {
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sirfsoc_uart_pio_tx_chars(sirfport,
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SIRFSOC_UART_IO_TX_REASONABLE_CNT);
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if ((uart_circ_empty(xmit)) &&
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(rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
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ufifo_st->ff_empty(port->line)))
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sirfsoc_uart_stop_tx(port);
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}
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}
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spin_unlock(&port->lock);
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return IRQ_HANDLED;
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}
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|
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static void sirfsoc_uart_start_rx(struct uart_port *port)
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{
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struct sirfsoc_uart_port *sirfport = to_sirfport(port);
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struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
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struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
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unsigned long regv;
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if (!sirfport->is_marco) {
|
|
regv = rd_regl(port, ureg->sirfsoc_int_en_reg);
|
|
wr_regl(port, ureg->sirfsoc_int_en_reg, regv |
|
|
SIRFUART_RX_IO_INT_EN(port, uint_en));
|
|
} else
|
|
wr_regl(port, ureg->sirfsoc_int_en_reg,
|
|
SIRFUART_RX_IO_INT_EN(port, uint_en));
|
|
wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
|
|
wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
|
|
wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START);
|
|
}
|
|
|
|
static unsigned int
|
|
sirfsoc_usp_calc_sample_div(unsigned long set_rate,
|
|
unsigned long ioclk_rate, unsigned long *sample_reg)
|
|
{
|
|
unsigned long min_delta = ~0UL;
|
|
unsigned short sample_div;
|
|
unsigned long ioclk_div = 0;
|
|
unsigned long temp_delta;
|
|
|
|
for (sample_div = SIRF_MIN_SAMPLE_DIV;
|
|
sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
|
|
temp_delta = ioclk_rate -
|
|
(ioclk_rate + (set_rate * sample_div) / 2)
|
|
/ (set_rate * sample_div) * set_rate * sample_div;
|
|
|
|
temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
|
|
if (temp_delta < min_delta) {
|
|
ioclk_div = (2 * ioclk_rate /
|
|
(set_rate * sample_div) + 1) / 2 - 1;
|
|
if (ioclk_div > SIRF_IOCLK_DIV_MAX)
|
|
continue;
|
|
min_delta = temp_delta;
|
|
*sample_reg = sample_div;
|
|
if (!temp_delta)
|
|
break;
|
|
}
|
|
}
|
|
return ioclk_div;
|
|
}
|
|
|
|
static unsigned int
|
|
sirfsoc_uart_calc_sample_div(unsigned long baud_rate,
|
|
unsigned long ioclk_rate, unsigned long *set_baud)
|
|
{
|
|
unsigned long min_delta = ~0UL;
|
|
unsigned short sample_div;
|
|
unsigned int regv = 0;
|
|
unsigned long ioclk_div;
|
|
unsigned long baud_tmp;
|
|
int temp_delta;
|
|
|
|
for (sample_div = SIRF_MIN_SAMPLE_DIV;
|
|
sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
|
|
ioclk_div = (ioclk_rate / (baud_rate * (sample_div + 1))) - 1;
|
|
if (ioclk_div > SIRF_IOCLK_DIV_MAX)
|
|
continue;
|
|
baud_tmp = ioclk_rate / ((ioclk_div + 1) * (sample_div + 1));
|
|
temp_delta = baud_tmp - baud_rate;
|
|
temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
|
|
if (temp_delta < min_delta) {
|
|
regv = regv & (~SIRF_IOCLK_DIV_MASK);
|
|
regv = regv | ioclk_div;
|
|
regv = regv & (~SIRF_SAMPLE_DIV_MASK);
|
|
regv = regv | (sample_div << SIRF_SAMPLE_DIV_SHIFT);
|
|
min_delta = temp_delta;
|
|
*set_baud = baud_tmp;
|
|
}
|
|
}
|
|
return regv;
|
|
}
|
|
|
|
static void sirfsoc_uart_set_termios(struct uart_port *port,
|
|
struct ktermios *termios,
|
|
struct ktermios *old)
|
|
{
|
|
struct sirfsoc_uart_port *sirfport = to_sirfport(port);
|
|
struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
|
|
struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
|
|
unsigned long config_reg = 0;
|
|
unsigned long baud_rate;
|
|
unsigned long set_baud;
|
|
unsigned long flags;
|
|
unsigned long ic;
|
|
unsigned int clk_div_reg = 0;
|
|
unsigned long temp_reg_val, ioclk_rate;
|
|
unsigned long rx_time_out;
|
|
int threshold_div;
|
|
int temp;
|
|
u32 data_bit_len, stop_bit_len, len_val;
|
|
unsigned long sample_div_reg = 0xf;
|
|
ioclk_rate = port->uartclk;
|
|
|
|
switch (termios->c_cflag & CSIZE) {
|
|
default:
|
|
case CS8:
|
|
data_bit_len = 8;
|
|
config_reg |= SIRFUART_DATA_BIT_LEN_8;
|
|
break;
|
|
case CS7:
|
|
data_bit_len = 7;
|
|
config_reg |= SIRFUART_DATA_BIT_LEN_7;
|
|
break;
|
|
case CS6:
|
|
data_bit_len = 6;
|
|
config_reg |= SIRFUART_DATA_BIT_LEN_6;
|
|
break;
|
|
case CS5:
|
|
data_bit_len = 5;
|
|
config_reg |= SIRFUART_DATA_BIT_LEN_5;
|
|
break;
|
|
}
|
|
if (termios->c_cflag & CSTOPB) {
|
|
config_reg |= SIRFUART_STOP_BIT_LEN_2;
|
|
stop_bit_len = 2;
|
|
} else
|
|
stop_bit_len = 1;
|
|
|
|
spin_lock_irqsave(&port->lock, flags);
|
|
port->read_status_mask = uint_en->sirfsoc_rx_oflow_en;
|
|
port->ignore_status_mask = 0;
|
|
if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
|
|
if (termios->c_iflag & INPCK)
|
|
port->read_status_mask |= uint_en->sirfsoc_frm_err_en |
|
|
uint_en->sirfsoc_parity_err_en;
|
|
} else {
|
|
if (termios->c_iflag & INPCK)
|
|
port->read_status_mask |= uint_en->sirfsoc_frm_err_en;
|
|
}
|
|
if (termios->c_iflag & (BRKINT | PARMRK))
|
|
port->read_status_mask |= uint_en->sirfsoc_rxd_brk_en;
|
|
if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
|
|
if (termios->c_iflag & IGNPAR)
|
|
port->ignore_status_mask |=
|
|
uint_en->sirfsoc_frm_err_en |
|
|
uint_en->sirfsoc_parity_err_en;
|
|
if (termios->c_cflag & PARENB) {
|
|
if (termios->c_cflag & CMSPAR) {
|
|
if (termios->c_cflag & PARODD)
|
|
config_reg |= SIRFUART_STICK_BIT_MARK;
|
|
else
|
|
config_reg |= SIRFUART_STICK_BIT_SPACE;
|
|
} else if (termios->c_cflag & PARODD) {
|
|
config_reg |= SIRFUART_STICK_BIT_ODD;
|
|
} else {
|
|
config_reg |= SIRFUART_STICK_BIT_EVEN;
|
|
}
|
|
}
|
|
} else {
|
|
if (termios->c_iflag & IGNPAR)
|
|
port->ignore_status_mask |=
|
|
uint_en->sirfsoc_frm_err_en;
|
|
if (termios->c_cflag & PARENB)
|
|
dev_warn(port->dev,
|
|
"USP-UART not support parity err\n");
|
|
}
|
|
if (termios->c_iflag & IGNBRK) {
|
|
port->ignore_status_mask |=
|
|
uint_en->sirfsoc_rxd_brk_en;
|
|
if (termios->c_iflag & IGNPAR)
|
|
port->ignore_status_mask |=
|
|
uint_en->sirfsoc_rx_oflow_en;
|
|
}
|
|
if ((termios->c_cflag & CREAD) == 0)
|
|
port->ignore_status_mask |= SIRFUART_DUMMY_READ;
|
|
/* Hardware Flow Control Settings */
|
|
if (UART_ENABLE_MS(port, termios->c_cflag)) {
|
|
if (!sirfport->ms_enabled)
|
|
sirfsoc_uart_enable_ms(port);
|
|
} else {
|
|
if (sirfport->ms_enabled)
|
|
sirfsoc_uart_disable_ms(port);
|
|
}
|
|
baud_rate = uart_get_baud_rate(port, termios, old, 0, 4000000);
|
|
if (ioclk_rate == 150000000) {
|
|
for (ic = 0; ic < SIRF_BAUD_RATE_SUPPORT_NR; ic++)
|
|
if (baud_rate == baudrate_to_regv[ic].baud_rate)
|
|
clk_div_reg = baudrate_to_regv[ic].reg_val;
|
|
}
|
|
set_baud = baud_rate;
|
|
if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
|
|
if (unlikely(clk_div_reg == 0))
|
|
clk_div_reg = sirfsoc_uart_calc_sample_div(baud_rate,
|
|
ioclk_rate, &set_baud);
|
|
wr_regl(port, ureg->sirfsoc_divisor, clk_div_reg);
|
|
} else {
|
|
clk_div_reg = sirfsoc_usp_calc_sample_div(baud_rate,
|
|
ioclk_rate, &sample_div_reg);
|
|
sample_div_reg--;
|
|
set_baud = ((ioclk_rate / (clk_div_reg+1) - 1) /
|
|
(sample_div_reg + 1));
|
|
/* setting usp mode 2 */
|
|
len_val = ((1 << 0) | (1 << 8));
|
|
len_val |= ((clk_div_reg & 0x3ff) << 21);
|
|
wr_regl(port, ureg->sirfsoc_mode2,
|
|
len_val);
|
|
|
|
}
|
|
if (tty_termios_baud_rate(termios))
|
|
tty_termios_encode_baud_rate(termios, set_baud, set_baud);
|
|
/* set receive timeout && data bits len */
|
|
rx_time_out = SIRFSOC_UART_RX_TIMEOUT(set_baud, 20000);
|
|
rx_time_out = SIRFUART_RECV_TIMEOUT_VALUE(rx_time_out);
|
|
temp_reg_val = rd_regl(port, ureg->sirfsoc_tx_fifo_op);
|
|
wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
|
|
wr_regl(port, ureg->sirfsoc_tx_fifo_op,
|
|
(temp_reg_val & ~SIRFUART_FIFO_START));
|
|
if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
|
|
config_reg |= SIRFUART_RECV_TIMEOUT(port, rx_time_out);
|
|
wr_regl(port, ureg->sirfsoc_line_ctrl, config_reg);
|
|
} else {
|
|
/*tx frame ctrl*/
|
|
len_val = (data_bit_len - 1) << 0;
|
|
len_val |= (data_bit_len + 1 + stop_bit_len - 1) << 16;
|
|
len_val |= ((data_bit_len - 1) << 24);
|
|
len_val |= (((clk_div_reg & 0xc00) >> 10) << 30);
|
|
wr_regl(port, ureg->sirfsoc_tx_frame_ctrl, len_val);
|
|
/*rx frame ctrl*/
|
|
len_val = (data_bit_len - 1) << 0;
|
|
len_val |= (data_bit_len + 1 + stop_bit_len - 1) << 8;
|
|
len_val |= (data_bit_len - 1) << 16;
|
|
len_val |= (((clk_div_reg & 0xf000) >> 12) << 24);
|
|
wr_regl(port, ureg->sirfsoc_rx_frame_ctrl, len_val);
|
|
/*async param*/
|
|
wr_regl(port, ureg->sirfsoc_async_param_reg,
|
|
(SIRFUART_RECV_TIMEOUT(port, rx_time_out)) |
|
|
(sample_div_reg & 0x3f) << 16);
|
|
}
|
|
wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, SIRFUART_IO_MODE);
|
|
wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, SIRFUART_IO_MODE);
|
|
/* Reset Rx/Tx FIFO Threshold level for proper baudrate */
|
|
if (set_baud < 1000000)
|
|
threshold_div = 1;
|
|
else
|
|
threshold_div = 2;
|
|
temp = SIRFUART_FIFO_THD(port);
|
|
wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl, temp / threshold_div);
|
|
wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl, temp / threshold_div);
|
|
temp_reg_val |= SIRFUART_FIFO_START;
|
|
wr_regl(port, ureg->sirfsoc_tx_fifo_op, temp_reg_val);
|
|
uart_update_timeout(port, termios->c_cflag, set_baud);
|
|
sirfsoc_uart_start_rx(port);
|
|
wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_TX_EN | SIRFUART_RX_EN);
|
|
spin_unlock_irqrestore(&port->lock, flags);
|
|
}
|
|
|
|
static void startup_uart_controller(struct uart_port *port)
|
|
{
|
|
struct sirfsoc_uart_port *sirfport = to_sirfport(port);
|
|
struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
|
|
unsigned long temp_regv;
|
|
int temp;
|
|
temp_regv = rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl);
|
|
wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, temp_regv |
|
|
SIRFUART_IO_MODE);
|
|
temp_regv = rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl);
|
|
wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, temp_regv |
|
|
SIRFUART_IO_MODE);
|
|
wr_regl(port, ureg->sirfsoc_tx_dma_io_len, 0);
|
|
wr_regl(port, ureg->sirfsoc_rx_dma_io_len, 0);
|
|
wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_RX_EN | SIRFUART_TX_EN);
|
|
if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
|
|
wr_regl(port, ureg->sirfsoc_mode1,
|
|
SIRFSOC_USP_ENDIAN_CTRL_LSBF |
|
|
SIRFSOC_USP_EN);
|
|
wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_RESET);
|
|
wr_regl(port, ureg->sirfsoc_tx_fifo_op, 0);
|
|
wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
|
|
wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
|
|
temp = SIRFUART_FIFO_THD(port);
|
|
wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl, temp);
|
|
wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl, temp);
|
|
}
|
|
|
|
static int sirfsoc_uart_startup(struct uart_port *port)
|
|
{
|
|
struct sirfsoc_uart_port *sirfport = to_sirfport(port);
|
|
unsigned int index = port->line;
|
|
int ret;
|
|
set_irq_flags(port->irq, IRQF_VALID | IRQF_NOAUTOEN);
|
|
ret = request_irq(port->irq,
|
|
sirfsoc_uart_isr,
|
|
0,
|
|
SIRFUART_PORT_NAME,
|
|
sirfport);
|
|
if (ret != 0) {
|
|
dev_err(port->dev, "UART%d request IRQ line (%d) failed.\n",
|
|
index, port->irq);
|
|
goto irq_err;
|
|
}
|
|
startup_uart_controller(port);
|
|
|
|
sirfport->ms_enabled = false;
|
|
if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
|
|
sirfport->hw_flow_ctrl) {
|
|
set_irq_flags(gpio_to_irq(sirfport->cts_gpio),
|
|
IRQF_VALID | IRQF_NOAUTOEN);
|
|
ret = request_irq(gpio_to_irq(sirfport->cts_gpio),
|
|
sirfsoc_uart_usp_cts_handler, IRQF_TRIGGER_FALLING |
|
|
IRQF_TRIGGER_RISING, "usp_cts_irq", sirfport);
|
|
if (ret != 0) {
|
|
dev_err(port->dev, "UART-USP:request gpio irq fail\n");
|
|
goto init_rx_err;
|
|
}
|
|
}
|
|
|
|
enable_irq(port->irq);
|
|
|
|
init_rx_err:
|
|
free_irq(port->irq, sirfport);
|
|
irq_err:
|
|
return ret;
|
|
}
|
|
|
|
static void sirfsoc_uart_shutdown(struct uart_port *port)
|
|
{
|
|
struct sirfsoc_uart_port *sirfport = to_sirfport(port);
|
|
struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
|
|
if (!sirfport->is_marco)
|
|
wr_regl(port, ureg->sirfsoc_int_en_reg, 0);
|
|
else
|
|
wr_regl(port, SIRFUART_INT_EN_CLR, ~0UL);
|
|
|
|
free_irq(port->irq, sirfport);
|
|
if (sirfport->ms_enabled)
|
|
sirfsoc_uart_disable_ms(port);
|
|
if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
|
|
sirfport->hw_flow_ctrl) {
|
|
gpio_set_value(sirfport->rts_gpio, 1);
|
|
free_irq(gpio_to_irq(sirfport->cts_gpio), sirfport);
|
|
}
|
|
}
|
|
|
|
static const char *sirfsoc_uart_type(struct uart_port *port)
|
|
{
|
|
return port->type == SIRFSOC_PORT_TYPE ? SIRFUART_PORT_NAME : NULL;
|
|
}
|
|
|
|
static int sirfsoc_uart_request_port(struct uart_port *port)
|
|
{
|
|
struct sirfsoc_uart_port *sirfport = to_sirfport(port);
|
|
struct sirfsoc_uart_param *uart_param = &sirfport->uart_reg->uart_param;
|
|
void *ret;
|
|
ret = request_mem_region(port->mapbase,
|
|
SIRFUART_MAP_SIZE, uart_param->port_name);
|
|
return ret ? 0 : -EBUSY;
|
|
}
|
|
|
|
static void sirfsoc_uart_release_port(struct uart_port *port)
|
|
{
|
|
release_mem_region(port->mapbase, SIRFUART_MAP_SIZE);
|
|
}
|
|
|
|
static void sirfsoc_uart_config_port(struct uart_port *port, int flags)
|
|
{
|
|
if (flags & UART_CONFIG_TYPE) {
|
|
port->type = SIRFSOC_PORT_TYPE;
|
|
sirfsoc_uart_request_port(port);
|
|
}
|
|
}
|
|
|
|
static struct uart_ops sirfsoc_uart_ops = {
|
|
.tx_empty = sirfsoc_uart_tx_empty,
|
|
.get_mctrl = sirfsoc_uart_get_mctrl,
|
|
.set_mctrl = sirfsoc_uart_set_mctrl,
|
|
.stop_tx = sirfsoc_uart_stop_tx,
|
|
.start_tx = sirfsoc_uart_start_tx,
|
|
.stop_rx = sirfsoc_uart_stop_rx,
|
|
.enable_ms = sirfsoc_uart_enable_ms,
|
|
.break_ctl = sirfsoc_uart_break_ctl,
|
|
.startup = sirfsoc_uart_startup,
|
|
.shutdown = sirfsoc_uart_shutdown,
|
|
.set_termios = sirfsoc_uart_set_termios,
|
|
.type = sirfsoc_uart_type,
|
|
.release_port = sirfsoc_uart_release_port,
|
|
.request_port = sirfsoc_uart_request_port,
|
|
.config_port = sirfsoc_uart_config_port,
|
|
};
|
|
|
|
#ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
|
|
static int __init
|
|
sirfsoc_uart_console_setup(struct console *co, char *options)
|
|
{
|
|
unsigned int baud = 115200;
|
|
unsigned int bits = 8;
|
|
unsigned int parity = 'n';
|
|
unsigned int flow = 'n';
|
|
struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
|
|
struct sirfsoc_uart_port *sirfport = to_sirfport(port);
|
|
struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
|
|
if (co->index < 0 || co->index >= SIRFSOC_UART_NR)
|
|
return -EINVAL;
|
|
|
|
if (!port->mapbase)
|
|
return -ENODEV;
|
|
|
|
/* enable usp in mode1 register */
|
|
if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
|
|
wr_regl(port, ureg->sirfsoc_mode1, SIRFSOC_USP_EN |
|
|
SIRFSOC_USP_ENDIAN_CTRL_LSBF);
|
|
if (options)
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
port->cons = co;
|
|
|
|
return uart_set_options(port, co, baud, parity, bits, flow);
|
|
}
|
|
|
|
static void sirfsoc_uart_console_putchar(struct uart_port *port, int ch)
|
|
{
|
|
struct sirfsoc_uart_port *sirfport = to_sirfport(port);
|
|
struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
|
|
struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
|
|
while (rd_regl(port,
|
|
ureg->sirfsoc_tx_fifo_status) & ufifo_st->ff_full(port->line))
|
|
cpu_relax();
|
|
wr_regb(port, ureg->sirfsoc_tx_fifo_data, ch);
|
|
}
|
|
|
|
static void sirfsoc_uart_console_write(struct console *co, const char *s,
|
|
unsigned int count)
|
|
{
|
|
struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
|
|
uart_console_write(port, s, count, sirfsoc_uart_console_putchar);
|
|
}
|
|
|
|
static struct console sirfsoc_uart_console = {
|
|
.name = SIRFSOC_UART_NAME,
|
|
.device = uart_console_device,
|
|
.flags = CON_PRINTBUFFER,
|
|
.index = -1,
|
|
.write = sirfsoc_uart_console_write,
|
|
.setup = sirfsoc_uart_console_setup,
|
|
.data = &sirfsoc_uart_drv,
|
|
};
|
|
|
|
static int __init sirfsoc_uart_console_init(void)
|
|
{
|
|
register_console(&sirfsoc_uart_console);
|
|
return 0;
|
|
}
|
|
console_initcall(sirfsoc_uart_console_init);
|
|
#endif
|
|
|
|
static struct uart_driver sirfsoc_uart_drv = {
|
|
.owner = THIS_MODULE,
|
|
.driver_name = SIRFUART_PORT_NAME,
|
|
.nr = SIRFSOC_UART_NR,
|
|
.dev_name = SIRFSOC_UART_NAME,
|
|
.major = SIRFSOC_UART_MAJOR,
|
|
.minor = SIRFSOC_UART_MINOR,
|
|
#ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
|
|
.cons = &sirfsoc_uart_console,
|
|
#else
|
|
.cons = NULL,
|
|
#endif
|
|
};
|
|
|
|
static struct of_device_id sirfsoc_uart_ids[] = {
|
|
{ .compatible = "sirf,prima2-uart", .data = &sirfsoc_uart,},
|
|
{ .compatible = "sirf,marco-uart", .data = &sirfsoc_uart},
|
|
{ .compatible = "sirf,prima2-usp-uart", .data = &sirfsoc_usp},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sirfsoc_uart_ids);
|
|
|
|
static int sirfsoc_uart_probe(struct platform_device *pdev)
|
|
{
|
|
struct sirfsoc_uart_port *sirfport;
|
|
struct uart_port *port;
|
|
struct resource *res;
|
|
int ret;
|
|
const struct of_device_id *match;
|
|
|
|
match = of_match_node(sirfsoc_uart_ids, pdev->dev.of_node);
|
|
if (of_property_read_u32(pdev->dev.of_node, "cell-index", &pdev->id)) {
|
|
dev_err(&pdev->dev,
|
|
"Unable to find cell-index in uart node.\n");
|
|
ret = -EFAULT;
|
|
goto err;
|
|
}
|
|
if (of_device_is_compatible(pdev->dev.of_node, "sirf,prima2-usp-uart"))
|
|
pdev->id += ((struct sirfsoc_uart_register *)
|
|
match->data)->uart_param.register_uart_nr;
|
|
sirfport = &sirfsoc_uart_ports[pdev->id];
|
|
port = &sirfport->port;
|
|
port->dev = &pdev->dev;
|
|
port->private_data = sirfport;
|
|
sirfport->uart_reg = (struct sirfsoc_uart_register *)match->data;
|
|
|
|
sirfport->hw_flow_ctrl = of_property_read_bool(pdev->dev.of_node,
|
|
"sirf,uart-has-rtscts");
|
|
if (of_device_is_compatible(pdev->dev.of_node, "sirf,prima2-uart"))
|
|
sirfport->uart_reg->uart_type = SIRF_REAL_UART;
|
|
if (of_device_is_compatible(pdev->dev.of_node, "sirf,prima2-usp-uart")) {
|
|
sirfport->uart_reg->uart_type = SIRF_USP_UART;
|
|
if (!sirfport->hw_flow_ctrl)
|
|
goto usp_no_flow_control;
|
|
if (of_find_property(pdev->dev.of_node, "cts-gpios", NULL))
|
|
sirfport->cts_gpio = of_get_named_gpio(
|
|
pdev->dev.of_node, "cts-gpios", 0);
|
|
else
|
|
sirfport->cts_gpio = -1;
|
|
if (of_find_property(pdev->dev.of_node, "rts-gpios", NULL))
|
|
sirfport->rts_gpio = of_get_named_gpio(
|
|
pdev->dev.of_node, "rts-gpios", 0);
|
|
else
|
|
sirfport->rts_gpio = -1;
|
|
|
|
if ((!gpio_is_valid(sirfport->cts_gpio) ||
|
|
!gpio_is_valid(sirfport->rts_gpio))) {
|
|
ret = -EINVAL;
|
|
dev_err(&pdev->dev,
|
|
"Usp flow control must have rfs and tfs gpio");
|
|
goto err;
|
|
}
|
|
ret = devm_gpio_request(&pdev->dev, sirfport->cts_gpio,
|
|
"usp-rfs-gpio");
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Unable request rfs gpio");
|
|
goto err;
|
|
}
|
|
gpio_direction_input(sirfport->cts_gpio);
|
|
ret = devm_gpio_request(&pdev->dev, sirfport->rts_gpio,
|
|
"usp-tfs-gpio");
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Unable request tfs gpio");
|
|
goto err;
|
|
}
|
|
gpio_direction_output(sirfport->rts_gpio, 1);
|
|
}
|
|
usp_no_flow_control:
|
|
if (of_device_is_compatible(pdev->dev.of_node, "sirf,marco-uart"))
|
|
sirfport->is_marco = true;
|
|
|
|
if (of_property_read_u32(pdev->dev.of_node,
|
|
"fifosize",
|
|
&port->fifosize)) {
|
|
dev_err(&pdev->dev,
|
|
"Unable to find fifosize in uart node.\n");
|
|
ret = -EFAULT;
|
|
goto err;
|
|
}
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (res == NULL) {
|
|
dev_err(&pdev->dev, "Insufficient resources.\n");
|
|
ret = -EFAULT;
|
|
goto err;
|
|
}
|
|
port->mapbase = res->start;
|
|
port->membase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
|
|
if (!port->membase) {
|
|
dev_err(&pdev->dev, "Cannot remap resource.\n");
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
if (res == NULL) {
|
|
dev_err(&pdev->dev, "Insufficient resources.\n");
|
|
ret = -EFAULT;
|
|
goto err;
|
|
}
|
|
port->irq = res->start;
|
|
|
|
sirfport->clk = clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(sirfport->clk)) {
|
|
ret = PTR_ERR(sirfport->clk);
|
|
goto err;
|
|
}
|
|
clk_prepare_enable(sirfport->clk);
|
|
port->uartclk = clk_get_rate(sirfport->clk);
|
|
|
|
port->ops = &sirfsoc_uart_ops;
|
|
spin_lock_init(&port->lock);
|
|
|
|
platform_set_drvdata(pdev, sirfport);
|
|
ret = uart_add_one_port(&sirfsoc_uart_drv, port);
|
|
if (ret != 0) {
|
|
dev_err(&pdev->dev, "Cannot add UART port(%d).\n", pdev->id);
|
|
goto port_err;
|
|
}
|
|
|
|
return 0;
|
|
|
|
port_err:
|
|
clk_disable_unprepare(sirfport->clk);
|
|
clk_put(sirfport->clk);
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
static int sirfsoc_uart_remove(struct platform_device *pdev)
|
|
{
|
|
struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
|
|
struct uart_port *port = &sirfport->port;
|
|
clk_disable_unprepare(sirfport->clk);
|
|
clk_put(sirfport->clk);
|
|
uart_remove_one_port(&sirfsoc_uart_drv, port);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
sirfsoc_uart_suspend(struct platform_device *pdev, pm_message_t state)
|
|
{
|
|
struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
|
|
struct uart_port *port = &sirfport->port;
|
|
uart_suspend_port(&sirfsoc_uart_drv, port);
|
|
return 0;
|
|
}
|
|
|
|
static int sirfsoc_uart_resume(struct platform_device *pdev)
|
|
{
|
|
struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
|
|
struct uart_port *port = &sirfport->port;
|
|
uart_resume_port(&sirfsoc_uart_drv, port);
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver sirfsoc_uart_driver = {
|
|
.probe = sirfsoc_uart_probe,
|
|
.remove = sirfsoc_uart_remove,
|
|
.suspend = sirfsoc_uart_suspend,
|
|
.resume = sirfsoc_uart_resume,
|
|
.driver = {
|
|
.name = SIRFUART_PORT_NAME,
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = sirfsoc_uart_ids,
|
|
},
|
|
};
|
|
|
|
static int __init sirfsoc_uart_init(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
ret = uart_register_driver(&sirfsoc_uart_drv);
|
|
if (ret)
|
|
goto out;
|
|
|
|
ret = platform_driver_register(&sirfsoc_uart_driver);
|
|
if (ret)
|
|
uart_unregister_driver(&sirfsoc_uart_drv);
|
|
out:
|
|
return ret;
|
|
}
|
|
module_init(sirfsoc_uart_init);
|
|
|
|
static void __exit sirfsoc_uart_exit(void)
|
|
{
|
|
platform_driver_unregister(&sirfsoc_uart_driver);
|
|
uart_unregister_driver(&sirfsoc_uart_drv);
|
|
}
|
|
module_exit(sirfsoc_uart_exit);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Bin Shi <Bin.Shi@csr.com>, Rong Wang<Rong.Wang@csr.com>");
|
|
MODULE_DESCRIPTION("CSR SiRFprimaII Uart Driver");
|