forked from Minki/linux
5d36a3321b
The patch allows Async3 clock source to be selected between PLL1 SYSCLK2 and PLL0 SYSCLK2. Having Async3 source from PLL1 SYSCLK2 allows peripherals on that domain to remain unaffected by frequency scaling on PLL0. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> |
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