Alban Bedel d25b4f65bf DEVICETREE: Add bindings for the ATH79 DDR controllers ... The DDR controller of the ARxxx and AR9xxx families provides an interface to flush the FIFO between various devices and the DDR. This is mainly used by the IRQ controller to flush the FIFO before running the interrupt handler of such devices. Signed-off-by: Alban Bedel <albeu@free.fr> Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2015-06-21 21:54:02 +02:00
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fsl	driver/memory:Move Freescale IFC driver to a common driver	2014-02-18 12:20:45 -08:00
ti
ath79-ddr-controller.txt	DEVICETREE: Add bindings for the ATH79 DDR controllers	2015-06-21 21:54:02 +02:00
ingenic,jz4780-nemc.txt	dt-bindings: memory-controllers: Add binding for jz4780-nemc	2015-03-26 23:51:36 +01:00
mvebu-devbus.txt	memory: mvebu-devbus: add a devbus, keep-config property	2014-04-29 13:17:10 +00:00
mvebu-sdram-controller.txt	Documentation: dt-bindings: minimal documentation for MVEBU SDRAM controller	2014-11-22 01:03:57 +00:00
nvidia,tegra-mc.txt	of: Add NVIDIA Tegra memory controller binding	2014-11-26 09:43:25 +01:00
renesas-memory-controllers.txt	ARM: shmobile: Add DT bindings for Renesas memory controllers	2015-01-15 08:53:50 +09:00
synopsys.txt	Documentation: devicetree: Add binding for Synopsys DDR controller	2014-09-16 12:55:05 +02:00
ti-aemif.txt	memory: ti-aemif: add bindings for AEMIF driver	2014-02-28 16:48:03 -08:00