forked from Minki/linux
042000b003
Adds the main PLL clock groups for SOCFPGA into device tree file
so that the clock framework to query the clock and clock rates
appropriately.
$cat /sys/kernel/debug/clk/clk_summary
clock enable_cnt prepare_cnt rate
---------------------------------------------------------------------
osc1 2 2 25000000
sdram_pll 0 0 400000000
s2f_usr2_clk 0 0 66666666
ddr_dq_clk 0 0 200000000
ddr_2x_dqs_clk 0 0 400000000
ddr_dqs_clk 0 0 200000000
periph_pll 2 2 500000000
s2f_usr1_clk 0 0 50000000
per_base_clk 4 4 100000000
per_nand_mmc_clk 0 0 25000000
per_qsi_clk 0 0 250000000
emac1_clk 1 1 125000000
emac0_clk 0 0 125000000
main_pll 1 1 1600000000
cfg_s2f_usr0_clk 0 0 100000000
main_nand_sdmmc_clk 0 0 100000000
main_qspi_clk 0 0 400000000
dbg_base_clk 0 0 400000000
mainclk 0 0 400000000
mpuclk 1 1 800000000
smp_twd 1 1 200000000
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
316 lines
7.0 KiB
Plaintext
316 lines
7.0 KiB
Plaintext
/*
|
|
* Copyright (C) 2012 Altera <www.altera.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
* (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|
|
/include/ "skeleton.dtsi"
|
|
|
|
/ {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
aliases {
|
|
ethernet0 = &gmac0;
|
|
serial0 = &uart0;
|
|
serial1 = &uart1;
|
|
timer0 = &timer0;
|
|
timer1 = &timer1;
|
|
timer2 = &timer2;
|
|
timer3 = &timer3;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
compatible = "arm,cortex-a9";
|
|
device_type = "cpu";
|
|
reg = <0>;
|
|
next-level-cache = <&L2>;
|
|
};
|
|
cpu@1 {
|
|
compatible = "arm,cortex-a9";
|
|
device_type = "cpu";
|
|
reg = <1>;
|
|
next-level-cache = <&L2>;
|
|
};
|
|
};
|
|
|
|
intc: intc@fffed000 {
|
|
compatible = "arm,cortex-a9-gic";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
reg = <0xfffed000 0x1000>,
|
|
<0xfffec100 0x100>;
|
|
};
|
|
|
|
soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "simple-bus";
|
|
device_type = "soc";
|
|
interrupt-parent = <&intc>;
|
|
ranges;
|
|
|
|
amba {
|
|
compatible = "arm,amba-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
pdma: pdma@ffe01000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0xffe01000 0x1000>;
|
|
interrupts = <0 180 4>;
|
|
#dma-cells = <1>;
|
|
#dma-channels = <8>;
|
|
#dma-requests = <32>;
|
|
};
|
|
};
|
|
|
|
clkmgr@ffd04000 {
|
|
compatible = "altr,clk-mgr";
|
|
reg = <0xffd04000 0x1000>;
|
|
|
|
clocks {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
osc: osc1 {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
};
|
|
|
|
main_pll: main_pll {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#clock-cells = <0>;
|
|
compatible = "altr,socfpga-pll-clock";
|
|
clocks = <&osc>;
|
|
reg = <0x40>;
|
|
|
|
mpuclk: mpuclk {
|
|
#clock-cells = <0>;
|
|
compatible = "altr,socfpga-perip-clk";
|
|
clocks = <&main_pll>;
|
|
fixed-divider = <2>;
|
|
reg = <0x48>;
|
|
};
|
|
|
|
mainclk: mainclk {
|
|
#clock-cells = <0>;
|
|
compatible = "altr,socfpga-perip-clk";
|
|
clocks = <&main_pll>;
|
|
fixed-divider = <4>;
|
|
reg = <0x4C>;
|
|
};
|
|
|
|
dbg_base_clk: dbg_base_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "altr,socfpga-perip-clk";
|
|
clocks = <&main_pll>;
|
|
fixed-divider = <4>;
|
|
reg = <0x50>;
|
|
};
|
|
|
|
main_qspi_clk: main_qspi_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "altr,socfpga-perip-clk";
|
|
clocks = <&main_pll>;
|
|
reg = <0x54>;
|
|
};
|
|
|
|
main_nand_sdmmc_clk: main_nand_sdmmc_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "altr,socfpga-perip-clk";
|
|
clocks = <&main_pll>;
|
|
reg = <0x58>;
|
|
};
|
|
|
|
cfg_s2f_usr0_clk: cfg_s2f_usr0_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "altr,socfpga-perip-clk";
|
|
clocks = <&main_pll>;
|
|
reg = <0x5C>;
|
|
};
|
|
};
|
|
|
|
periph_pll: periph_pll {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#clock-cells = <0>;
|
|
compatible = "altr,socfpga-pll-clock";
|
|
clocks = <&osc>;
|
|
reg = <0x80>;
|
|
|
|
emac0_clk: emac0_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "altr,socfpga-perip-clk";
|
|
clocks = <&periph_pll>;
|
|
reg = <0x88>;
|
|
};
|
|
|
|
emac1_clk: emac1_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "altr,socfpga-perip-clk";
|
|
clocks = <&periph_pll>;
|
|
reg = <0x8C>;
|
|
};
|
|
|
|
per_qspi_clk: per_qsi_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "altr,socfpga-perip-clk";
|
|
clocks = <&periph_pll>;
|
|
reg = <0x90>;
|
|
};
|
|
|
|
per_nand_mmc_clk: per_nand_mmc_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "altr,socfpga-perip-clk";
|
|
clocks = <&periph_pll>;
|
|
reg = <0x94>;
|
|
};
|
|
|
|
per_base_clk: per_base_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "altr,socfpga-perip-clk";
|
|
clocks = <&periph_pll>;
|
|
reg = <0x98>;
|
|
};
|
|
|
|
s2f_usr1_clk: s2f_usr1_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "altr,socfpga-perip-clk";
|
|
clocks = <&periph_pll>;
|
|
reg = <0x9C>;
|
|
};
|
|
};
|
|
|
|
sdram_pll: sdram_pll {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#clock-cells = <0>;
|
|
compatible = "altr,socfpga-pll-clock";
|
|
clocks = <&osc>;
|
|
reg = <0xC0>;
|
|
|
|
ddr_dqs_clk: ddr_dqs_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "altr,socfpga-perip-clk";
|
|
clocks = <&sdram_pll>;
|
|
reg = <0xC8>;
|
|
};
|
|
|
|
ddr_2x_dqs_clk: ddr_2x_dqs_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "altr,socfpga-perip-clk";
|
|
clocks = <&sdram_pll>;
|
|
reg = <0xCC>;
|
|
};
|
|
|
|
ddr_dq_clk: ddr_dq_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "altr,socfpga-perip-clk";
|
|
clocks = <&sdram_pll>;
|
|
reg = <0xD0>;
|
|
};
|
|
|
|
s2f_usr2_clk: s2f_usr2_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "altr,socfpga-perip-clk";
|
|
clocks = <&sdram_pll>;
|
|
reg = <0xD4>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
gmac0: stmmac@ff700000 {
|
|
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
|
|
reg = <0xff700000 0x2000>;
|
|
interrupts = <0 115 4>;
|
|
interrupt-names = "macirq";
|
|
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
|
|
phy-mode = "gmii";
|
|
};
|
|
|
|
L2: l2-cache@fffef000 {
|
|
compatible = "arm,pl310-cache";
|
|
reg = <0xfffef000 0x1000>;
|
|
interrupts = <0 38 0x04>;
|
|
cache-unified;
|
|
cache-level = <2>;
|
|
};
|
|
|
|
/* Local timer */
|
|
timer@fffec600 {
|
|
compatible = "arm,cortex-a9-twd-timer";
|
|
reg = <0xfffec600 0x100>;
|
|
interrupts = <1 13 0xf04>;
|
|
};
|
|
|
|
timer0: timer0@ffc08000 {
|
|
compatible = "snps,dw-apb-timer-sp";
|
|
interrupts = <0 167 4>;
|
|
reg = <0xffc08000 0x1000>;
|
|
};
|
|
|
|
timer1: timer1@ffc09000 {
|
|
compatible = "snps,dw-apb-timer-sp";
|
|
interrupts = <0 168 4>;
|
|
reg = <0xffc09000 0x1000>;
|
|
};
|
|
|
|
timer2: timer2@ffd00000 {
|
|
compatible = "snps,dw-apb-timer-osc";
|
|
interrupts = <0 169 4>;
|
|
reg = <0xffd00000 0x1000>;
|
|
};
|
|
|
|
timer3: timer3@ffd01000 {
|
|
compatible = "snps,dw-apb-timer-osc";
|
|
interrupts = <0 170 4>;
|
|
reg = <0xffd01000 0x1000>;
|
|
};
|
|
|
|
uart0: serial0@ffc02000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0xffc02000 0x1000>;
|
|
interrupts = <0 162 4>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
};
|
|
|
|
uart1: serial1@ffc03000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0xffc03000 0x1000>;
|
|
interrupts = <0 163 4>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
};
|
|
|
|
rstmgr@ffd05000 {
|
|
compatible = "altr,rst-mgr";
|
|
reg = <0xffd05000 0x1000>;
|
|
};
|
|
|
|
sysmgr@ffd08000 {
|
|
compatible = "altr,sys-mgr";
|
|
reg = <0xffd08000 0x4000>;
|
|
};
|
|
};
|
|
};
|