forked from Minki/linux
b3a5af435a
This is the usual large batch of DT updates. Lots and lots of smaller changes, some of the larger ones to point out are: - Rockchip veyron (Chromebook) support, as well as several other new boards - DRM support on Atmel AT91SAM9N12EK - USB additions on some Allwinner platforms - Mediatek MT6580 support - Freescale i.MX6UL support - Cleanups for Renesas shmobile platforms - Lots of added devices on LPC18xx - Lots of added devices and boards on UniPhier There's also some dependent code added here, in particular some branches that are primarily merged through the clock tree. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJV5OMWAAoJEIwa5zzehBx3r2QP/1skn0zzgfvbK0kkPOh9q3Jk jX1elN4Wde1SnScz8UbdVb9nmdbhxsuYE/3+Lz7yCndWScBiak4qcsNHrSRhh3FA ST7Ub8DLc2TxY9K7eDkyVCcNkP35+UQTHCN76R5Lgrlfw3UO9Zr3xPFX3+Kd6aWz 9X8UnvJacQQIN/vO6J02kB96sKPEIANfuMgO6vDSbmcZ1RrdlHzjoRwAV0smECtJ NyOh+NQdPBR0gSl/peyKzAXoDHNXpDotltTmIz3tPA+dYBO/qG//B73H/oqox0ql AKAktyaDzdxXEuixPtAroo4dDy3xuIQ6xU+DNhPWQq0BgaxHWqkwq60d74ot8vCz 8gvC8pwA6gavbqVFNePOnwPNSyWZX01scX4fp903NjVM8/rGPvCR4y6p8lFIyVkG P0L8rmY/UYq3fieaAb1W0odASDrQpgg3zsHD7to43hz6jaRnMRCpA8nTVqJcyHqI E6YfGQH87Kpbvkjo0FYqo5P6xCCRTq+QUys6JruNYg05R/gd8AG7cXaVNO3yvg3T lRwNXDBt/zcp2exKnGR0IdGMUMICzsuoB8ZePkQdIWwePrd4AzT5qYJe/txmg1rd q+9VJqQkeF+txLd9XUV2W/Hcuzu3ZPCbs97I9tTKQHMGwKUZaPfuk2r4+4K+Ps5a dYwdms39p6AIT43rK+m3 =D2Pm -----END PGP SIGNATURE----- Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "Ladies and gentlemen, we proudly announce to you the latest branch of ARM device tree contents for the mainline kernel. Come and see, come and see! No less than twentythree thousand lines of additions! Just imagine the joy you will have of using your mainline kernel on newly supported hardware such as Rockchip Chromebooks, Freescale i.MX6UL boards or UniPhier hardware! For those of you feeling less adventurous, added hardware support on platforms such as TI DM814x and Gumstix Overo platforms might be more of your liking. We've got something for everyone here! Ahem. Cough. So, anyway... This is the usual large batch of DT updates. Lots and lots of smaller changes, some of the larger ones to point out are: - Rockchip veyron (Chromebook) support, as well as several other new boards - DRM support on Atmel AT91SAM9N12EK - USB additions on some Allwinner platforms - Mediatek MT6580 support - Freescale i.MX6UL support - cleanups for Renesas shmobile platforms - lots of added devices on LPC18xx - lots of added devices and boards on UniPhier There's also some dependent code added here, in particular some branches that are primarily merged through the clock tree" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (389 commits) ARM: tegra: Add gpio-ranges property ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114 ARM: tegra: Add Tegra124 PMU support ARM: tegra: jetson-tk1: Add GK20A GPU DT node ARM: tegra: venice2: Add GK20A GPU DT node ARM: tegra: Add IOMMU node to GK20A ARM: tegra: Add CPU regulator to the Jetson TK1 device tree ARM: tegra: Add entries for cpufreq on Tegra124 ARM: tegra: Enable the DFLL on the Jetson TK1 ARM: tegra: Add the DFLL to Tegra124 device tree ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset controller. ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes ARM: dts: rockchip: correct regulator power states for suspend ARM: dts: rockchip: correct regulator PM properties ARM: dts: vexpress: Use assigned-clock-parents for sp810 pinctrl: tegra: Only set the gpio range if needed arm: boot: dts: am4372: add ARM timers and SCU nodes ARM: dts: AM4372: Add the am4372-rtc compatible string ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain ...
673 lines
17 KiB
Plaintext
673 lines
17 KiB
Plaintext
/*
|
|
* Copyright 2014 Chen-Yu Tsai
|
|
*
|
|
* Chen-Yu Tsai <wens@csie.org>
|
|
*
|
|
* This file is dual-licensed: you can use it either under the terms
|
|
* of the GPL or the X11 license, at your option. Note that this dual
|
|
* licensing only applies to this file, and not this project as a
|
|
* whole.
|
|
*
|
|
* a) This file is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of the
|
|
* License, or (at your option) any later version.
|
|
*
|
|
* This file is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* Or, alternatively,
|
|
*
|
|
* b) Permission is hereby granted, free of charge, to any person
|
|
* obtaining a copy of this software and associated documentation
|
|
* files (the "Software"), to deal in the Software without
|
|
* restriction, including without limitation the rights to use,
|
|
* copy, modify, merge, publish, distribute, sublicense, and/or
|
|
* sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following
|
|
* conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be
|
|
* included in all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
|
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
|
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
|
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
* OTHER DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#include "skeleton.dtsi"
|
|
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
#include <dt-bindings/pinctrl/sun4i-a10.h>
|
|
|
|
/ {
|
|
interrupt-parent = <&gic>;
|
|
|
|
chosen {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
framebuffer@0 {
|
|
compatible = "allwinner,simple-framebuffer",
|
|
"simple-framebuffer";
|
|
allwinner,pipeline = "de_be0-lcd0";
|
|
clocks = <&pll6 0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv7-timer";
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
clock-frequency = <24000000>;
|
|
arm,cpu-registers-not-fw-configured;
|
|
};
|
|
|
|
cpus {
|
|
enable-method = "allwinner,sun8i-a23";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
compatible = "arm,cortex-a7";
|
|
device_type = "cpu";
|
|
reg = <0>;
|
|
};
|
|
|
|
cpu@1 {
|
|
compatible = "arm,cortex-a7";
|
|
device_type = "cpu";
|
|
reg = <1>;
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
osc24M: osc24M_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <24000000>;
|
|
clock-output-names = "osc24M";
|
|
};
|
|
|
|
osc32k: osc32k_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32768>;
|
|
clock-output-names = "osc32k";
|
|
};
|
|
|
|
pll1: clk@01c20000 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun8i-a23-pll1-clk";
|
|
reg = <0x01c20000 0x4>;
|
|
clocks = <&osc24M>;
|
|
clock-output-names = "pll1";
|
|
};
|
|
|
|
/* dummy clock until actually implemented */
|
|
pll5: pll5_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0>;
|
|
clock-output-names = "pll5";
|
|
};
|
|
|
|
pll6: clk@01c20028 {
|
|
#clock-cells = <1>;
|
|
compatible = "allwinner,sun6i-a31-pll6-clk";
|
|
reg = <0x01c20028 0x4>;
|
|
clocks = <&osc24M>;
|
|
clock-output-names = "pll6", "pll6x2";
|
|
};
|
|
|
|
cpu: cpu_clk@01c20050 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-cpu-clk";
|
|
reg = <0x01c20050 0x4>;
|
|
|
|
/*
|
|
* PLL1 is listed twice here.
|
|
* While it looks suspicious, it's actually documented
|
|
* that way both in the datasheet and in the code from
|
|
* Allwinner.
|
|
*/
|
|
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
|
|
clock-output-names = "cpu";
|
|
};
|
|
|
|
axi: axi_clk@01c20050 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun8i-a23-axi-clk";
|
|
reg = <0x01c20050 0x4>;
|
|
clocks = <&cpu>;
|
|
clock-output-names = "axi";
|
|
};
|
|
|
|
ahb1: ahb1_clk@01c20054 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun6i-a31-ahb1-clk";
|
|
reg = <0x01c20054 0x4>;
|
|
clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
|
|
clock-output-names = "ahb1";
|
|
};
|
|
|
|
apb1: apb1_clk@01c20054 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-apb0-clk";
|
|
reg = <0x01c20054 0x4>;
|
|
clocks = <&ahb1>;
|
|
clock-output-names = "apb1";
|
|
};
|
|
|
|
ahb1_gates: clk@01c20060 {
|
|
#clock-cells = <1>;
|
|
compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
|
|
reg = <0x01c20060 0x8>;
|
|
clocks = <&ahb1>;
|
|
clock-indices = <1>, <6>,
|
|
<8>, <9>, <10>,
|
|
<13>, <14>,
|
|
<19>, <20>,
|
|
<21>, <24>, <26>,
|
|
<29>, <32>, <36>,
|
|
<40>, <44>, <46>,
|
|
<52>, <54>,
|
|
<57>;
|
|
clock-output-names = "ahb1_mipidsi", "ahb1_dma",
|
|
"ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
|
|
"ahb1_nand", "ahb1_sdram",
|
|
"ahb1_hstimer", "ahb1_spi0",
|
|
"ahb1_spi1", "ahb1_otg", "ahb1_ehci",
|
|
"ahb1_ohci", "ahb1_ve", "ahb1_lcd",
|
|
"ahb1_csi", "ahb1_be", "ahb1_fe",
|
|
"ahb1_gpu", "ahb1_spinlock",
|
|
"ahb1_drc";
|
|
};
|
|
|
|
apb1_gates: clk@01c20068 {
|
|
#clock-cells = <1>;
|
|
compatible = "allwinner,sun8i-a23-apb1-gates-clk";
|
|
reg = <0x01c20068 0x4>;
|
|
clocks = <&apb1>;
|
|
clock-indices = <0>, <5>,
|
|
<12>, <13>;
|
|
clock-output-names = "apb1_codec", "apb1_pio",
|
|
"apb1_daudio0", "apb1_daudio1";
|
|
};
|
|
|
|
apb2: clk@01c20058 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-apb1-clk";
|
|
reg = <0x01c20058 0x4>;
|
|
clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
|
|
clock-output-names = "apb2";
|
|
};
|
|
|
|
apb2_gates: clk@01c2006c {
|
|
#clock-cells = <1>;
|
|
compatible = "allwinner,sun8i-a23-apb2-gates-clk";
|
|
reg = <0x01c2006c 0x4>;
|
|
clocks = <&apb2>;
|
|
clock-indices = <0>, <1>,
|
|
<2>, <16>,
|
|
<17>, <18>,
|
|
<19>, <20>;
|
|
clock-output-names = "apb2_i2c0", "apb2_i2c1",
|
|
"apb2_i2c2", "apb2_uart0",
|
|
"apb2_uart1", "apb2_uart2",
|
|
"apb2_uart3", "apb2_uart4";
|
|
};
|
|
|
|
mmc0_clk: clk@01c20088 {
|
|
#clock-cells = <1>;
|
|
compatible = "allwinner,sun4i-a10-mmc-clk";
|
|
reg = <0x01c20088 0x4>;
|
|
clocks = <&osc24M>, <&pll6 0>;
|
|
clock-output-names = "mmc0",
|
|
"mmc0_output",
|
|
"mmc0_sample";
|
|
};
|
|
|
|
mmc1_clk: clk@01c2008c {
|
|
#clock-cells = <1>;
|
|
compatible = "allwinner,sun4i-a10-mmc-clk";
|
|
reg = <0x01c2008c 0x4>;
|
|
clocks = <&osc24M>, <&pll6 0>;
|
|
clock-output-names = "mmc1",
|
|
"mmc1_output",
|
|
"mmc1_sample";
|
|
};
|
|
|
|
mmc2_clk: clk@01c20090 {
|
|
#clock-cells = <1>;
|
|
compatible = "allwinner,sun4i-a10-mmc-clk";
|
|
reg = <0x01c20090 0x4>;
|
|
clocks = <&osc24M>, <&pll6 0>;
|
|
clock-output-names = "mmc2",
|
|
"mmc2_output",
|
|
"mmc2_sample";
|
|
};
|
|
|
|
usb_clk: clk@01c200cc {
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
compatible = "allwinner,sun8i-a23-usb-clk";
|
|
reg = <0x01c200cc 0x4>;
|
|
clocks = <&osc24M>;
|
|
clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic",
|
|
"usb_hsic_12M", "usb_ohci0";
|
|
};
|
|
};
|
|
|
|
soc@01c00000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
dma: dma-controller@01c02000 {
|
|
compatible = "allwinner,sun8i-a23-dma";
|
|
reg = <0x01c02000 0x1000>;
|
|
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb1_gates 6>;
|
|
resets = <&ahb1_rst 6>;
|
|
#dma-cells = <1>;
|
|
};
|
|
|
|
mmc0: mmc@01c0f000 {
|
|
compatible = "allwinner,sun5i-a13-mmc";
|
|
reg = <0x01c0f000 0x1000>;
|
|
clocks = <&ahb1_gates 8>,
|
|
<&mmc0_clk 0>,
|
|
<&mmc0_clk 1>,
|
|
<&mmc0_clk 2>;
|
|
clock-names = "ahb",
|
|
"mmc",
|
|
"output",
|
|
"sample";
|
|
resets = <&ahb1_rst 8>;
|
|
reset-names = "ahb";
|
|
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
mmc1: mmc@01c10000 {
|
|
compatible = "allwinner,sun5i-a13-mmc";
|
|
reg = <0x01c10000 0x1000>;
|
|
clocks = <&ahb1_gates 9>,
|
|
<&mmc1_clk 0>,
|
|
<&mmc1_clk 1>,
|
|
<&mmc1_clk 2>;
|
|
clock-names = "ahb",
|
|
"mmc",
|
|
"output",
|
|
"sample";
|
|
resets = <&ahb1_rst 9>;
|
|
reset-names = "ahb";
|
|
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
mmc2: mmc@01c11000 {
|
|
compatible = "allwinner,sun5i-a13-mmc";
|
|
reg = <0x01c11000 0x1000>;
|
|
clocks = <&ahb1_gates 10>,
|
|
<&mmc2_clk 0>,
|
|
<&mmc2_clk 1>,
|
|
<&mmc2_clk 2>;
|
|
clock-names = "ahb",
|
|
"mmc",
|
|
"output",
|
|
"sample";
|
|
resets = <&ahb1_rst 10>;
|
|
reset-names = "ahb";
|
|
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
ehci0: usb@01c1a000 {
|
|
compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
|
|
reg = <0x01c1a000 0x100>;
|
|
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb1_gates 26>;
|
|
resets = <&ahb1_rst 26>;
|
|
phys = <&usbphy 1>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci0: usb@01c1a400 {
|
|
compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
|
|
reg = <0x01c1a400 0x100>;
|
|
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb1_gates 29>, <&usb_clk 16>;
|
|
resets = <&ahb1_rst 29>;
|
|
phys = <&usbphy 1>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
pio: pinctrl@01c20800 {
|
|
/* compatible gets set in SoC specific dtsi file */
|
|
reg = <0x01c20800 0x400>;
|
|
/* interrupts get set in SoC specific dtsi file */
|
|
clocks = <&apb1_gates 5>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#gpio-cells = <3>;
|
|
|
|
uart0_pins_a: uart0@0 {
|
|
allwinner,pins = "PF2", "PF4";
|
|
allwinner,function = "uart0";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
mmc0_pins_a: mmc0@0 {
|
|
allwinner,pins = "PF0", "PF1", "PF2",
|
|
"PF3", "PF4", "PF5";
|
|
allwinner,function = "mmc0";
|
|
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
mmc1_pins_a: mmc1@0 {
|
|
allwinner,pins = "PG0", "PG1", "PG2",
|
|
"PG3", "PG4", "PG5";
|
|
allwinner,function = "mmc1";
|
|
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
mmc2_8bit_pins: mmc2_8bit {
|
|
allwinner,pins = "PC5", "PC6", "PC8",
|
|
"PC9", "PC10", "PC11",
|
|
"PC12", "PC13", "PC14",
|
|
"PC15";
|
|
allwinner,function = "mmc2";
|
|
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
i2c0_pins_a: i2c0@0 {
|
|
allwinner,pins = "PH2", "PH3";
|
|
allwinner,function = "i2c0";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
i2c1_pins_a: i2c1@0 {
|
|
allwinner,pins = "PH4", "PH5";
|
|
allwinner,function = "i2c1";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
i2c2_pins_a: i2c2@0 {
|
|
allwinner,pins = "PE12", "PE13";
|
|
allwinner,function = "i2c2";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
};
|
|
|
|
ahb1_rst: reset@01c202c0 {
|
|
#reset-cells = <1>;
|
|
compatible = "allwinner,sun6i-a31-clock-reset";
|
|
reg = <0x01c202c0 0xc>;
|
|
};
|
|
|
|
apb1_rst: reset@01c202d0 {
|
|
#reset-cells = <1>;
|
|
compatible = "allwinner,sun6i-a31-clock-reset";
|
|
reg = <0x01c202d0 0x4>;
|
|
};
|
|
|
|
apb2_rst: reset@01c202d8 {
|
|
#reset-cells = <1>;
|
|
compatible = "allwinner,sun6i-a31-clock-reset";
|
|
reg = <0x01c202d8 0x4>;
|
|
};
|
|
|
|
timer@01c20c00 {
|
|
compatible = "allwinner,sun4i-a10-timer";
|
|
reg = <0x01c20c00 0xa0>;
|
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&osc24M>;
|
|
};
|
|
|
|
wdt0: watchdog@01c20ca0 {
|
|
compatible = "allwinner,sun6i-a31-wdt";
|
|
reg = <0x01c20ca0 0x20>;
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
lradc: lradc@01c22800 {
|
|
compatible = "allwinner,sun4i-a10-lradc-keys";
|
|
reg = <0x01c22800 0x100>;
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart0: serial@01c28000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28000 0x400>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb2_gates 16>;
|
|
resets = <&apb2_rst 16>;
|
|
dmas = <&dma 6>, <&dma 6>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@01c28400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28400 0x400>;
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb2_gates 17>;
|
|
resets = <&apb2_rst 17>;
|
|
dmas = <&dma 7>, <&dma 7>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@01c28800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28800 0x400>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb2_gates 18>;
|
|
resets = <&apb2_rst 18>;
|
|
dmas = <&dma 8>, <&dma 8>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@01c28c00 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28c00 0x400>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb2_gates 19>;
|
|
resets = <&apb2_rst 19>;
|
|
dmas = <&dma 9>, <&dma 9>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@01c29000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29000 0x400>;
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb2_gates 20>;
|
|
resets = <&apb2_rst 20>;
|
|
dmas = <&dma 10>, <&dma 10>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@01c2ac00 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2ac00 0x400>;
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb2_gates 0>;
|
|
resets = <&apb2_rst 0>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c1: i2c@01c2b000 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2b000 0x400>;
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb2_gates 1>;
|
|
resets = <&apb2_rst 1>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c2: i2c@01c2b400 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2b400 0x400>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb2_gates 2>;
|
|
resets = <&apb2_rst 2>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
gic: interrupt-controller@01c81000 {
|
|
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
|
|
reg = <0x01c81000 0x1000>,
|
|
<0x01c82000 0x1000>,
|
|
<0x01c84000 0x2000>,
|
|
<0x01c86000 0x2000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
rtc: rtc@01f00000 {
|
|
compatible = "allwinner,sun6i-a31-rtc";
|
|
reg = <0x01f00000 0x54>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
prcm@01f01400 {
|
|
compatible = "allwinner,sun8i-a23-prcm";
|
|
reg = <0x01f01400 0x200>;
|
|
|
|
ar100: ar100_clk {
|
|
compatible = "fixed-factor-clock";
|
|
#clock-cells = <0>;
|
|
clock-div = <1>;
|
|
clock-mult = <1>;
|
|
clocks = <&osc24M>;
|
|
clock-output-names = "ar100";
|
|
};
|
|
|
|
ahb0: ahb0_clk {
|
|
compatible = "fixed-factor-clock";
|
|
#clock-cells = <0>;
|
|
clock-div = <1>;
|
|
clock-mult = <1>;
|
|
clocks = <&ar100>;
|
|
clock-output-names = "ahb0";
|
|
};
|
|
|
|
apb0: apb0_clk {
|
|
compatible = "allwinner,sun8i-a23-apb0-clk";
|
|
#clock-cells = <0>;
|
|
clocks = <&ahb0>;
|
|
clock-output-names = "apb0";
|
|
};
|
|
|
|
apb0_gates: apb0_gates_clk {
|
|
compatible = "allwinner,sun8i-a23-apb0-gates-clk";
|
|
#clock-cells = <1>;
|
|
clocks = <&apb0>;
|
|
clock-output-names = "apb0_pio", "apb0_timer",
|
|
"apb0_rsb", "apb0_uart",
|
|
"apb0_i2c";
|
|
};
|
|
|
|
apb0_rst: apb0_rst {
|
|
compatible = "allwinner,sun6i-a31-clock-reset";
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
|
|
cpucfg@01f01c00 {
|
|
compatible = "allwinner,sun8i-a23-cpuconfig";
|
|
reg = <0x01f01c00 0x300>;
|
|
};
|
|
|
|
r_uart: serial@01f02800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01f02800 0x400>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb0_gates 4>;
|
|
resets = <&apb0_rst 4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
r_pio: pinctrl@01f02c00 {
|
|
compatible = "allwinner,sun8i-a23-r-pinctrl";
|
|
reg = <0x01f02c00 0x400>;
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb0_gates 0>;
|
|
resets = <&apb0_rst 0>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#gpio-cells = <3>;
|
|
|
|
r_uart_pins_a: r_uart@0 {
|
|
allwinner,pins = "PL2", "PL3";
|
|
allwinner,function = "s_uart";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
};
|
|
};
|
|
};
|