Valentin Longchamp 2ccf80b756 soc/fsl/qe: round brg_freq to 1kHz granularity ... Because of integer computation rounding in u-boot (that sets the QE brg-frequency DTS prop), the clk value is 99999999 Hz even though it is 100 MHz. When setting brg clks that are exact divisors of 100 MHz, this small differnce plays a role and can result in lower clks to be output (for instance 20 MHz - divide by 5 - results in 16.666 MHz - divide by 6). This patch fixes that by "forcing" the brg_clk to the nearest kHz when the difference is below 2 integer rounding errors (i.e. 4). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Scott Wood <oss@buserror.net>		2017-04-30 01:31:51 -05:00
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gpio.c	soc/fsl/qe: fix gpio save_regs functions	2016-09-25 02:38:56 -05:00
Kconfig	fsl/qe: Add QE TDM lib	2016-06-07 15:56:31 -07:00
Makefile	fsl/qe: Add QE TDM lib	2016-06-07 15:56:31 -07:00
qe_common.c	soc/fsl/qe: fix Oops on CPM1 (and likely CPM2)	2016-09-25 02:38:52 -05:00
qe_ic.c	qe/ic: fix a buffer overflow error and add check elsewhere	2016-03-09 10:44:12 -06:00
qe_ic.h
qe_io.c
qe_tdm.c	fsl/qe: use of_property_read_bool	2016-09-25 02:38:51 -05:00
qe.c	soc/fsl/qe: round brg_freq to 1kHz granularity	2017-04-30 01:31:51 -05:00
ucc_fast.c	fsl/qe: setup clock source for TDM mode	2016-06-07 15:56:30 -07:00
ucc_slow.c
ucc.c	fsl/qe: setup clock source for TDM mode	2016-06-07 15:56:30 -07:00
usb.c