forked from Minki/linux
0e530747c6
As per the existing implementation; implement the new one using
smp_mb().
AFAICT the s390 compare-and-swap does imply a barrier, however there
are some immediate ops that seem to be singly-copy atomic and do not
imply a barrier. One such is the "ni" op (which would be
and-immediate) which is used for the constant clear_bit
implementation. Therefore s390 needs full barriers for the
{before,after} atomic ops.
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/n/tip-kme5dz5hcobpnufnnkh1ech2@git.kernel.org
Cc: Chen Gang <gang.chen@asianux.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux390@de.ibm.com
Cc: linux-kernel@vger.kernel.org
Cc: linux-s390@vger.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
416 lines
9.2 KiB
C
416 lines
9.2 KiB
C
/*
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* Copyright IBM Corp. 1999, 2009
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* Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
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* Denis Joseph Barrow,
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* Arnd Bergmann <arndb@de.ibm.com>,
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*
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* Atomic operations that C can't guarantee us.
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* Useful for resource counting etc.
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* s390 uses 'Compare And Swap' for atomicity in SMP environment.
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*
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*/
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#ifndef __ARCH_S390_ATOMIC__
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#define __ARCH_S390_ATOMIC__
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <asm/barrier.h>
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#include <asm/cmpxchg.h>
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#define ATOMIC_INIT(i) { (i) }
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#define __ATOMIC_NO_BARRIER "\n"
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#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
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#define __ATOMIC_OR "lao"
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#define __ATOMIC_AND "lan"
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#define __ATOMIC_ADD "laa"
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#define __ATOMIC_BARRIER "bcr 14,0\n"
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#define __ATOMIC_LOOP(ptr, op_val, op_string, __barrier) \
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({ \
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int old_val; \
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\
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typecheck(atomic_t *, ptr); \
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asm volatile( \
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__barrier \
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op_string " %0,%2,%1\n" \
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__barrier \
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: "=d" (old_val), "+Q" ((ptr)->counter) \
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: "d" (op_val) \
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: "cc", "memory"); \
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old_val; \
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})
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#else /* CONFIG_HAVE_MARCH_Z196_FEATURES */
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#define __ATOMIC_OR "or"
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#define __ATOMIC_AND "nr"
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#define __ATOMIC_ADD "ar"
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#define __ATOMIC_BARRIER "\n"
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#define __ATOMIC_LOOP(ptr, op_val, op_string, __barrier) \
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({ \
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int old_val, new_val; \
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\
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typecheck(atomic_t *, ptr); \
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asm volatile( \
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" l %0,%2\n" \
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"0: lr %1,%0\n" \
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op_string " %1,%3\n" \
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" cs %0,%1,%2\n" \
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" jl 0b" \
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: "=&d" (old_val), "=&d" (new_val), "+Q" ((ptr)->counter)\
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: "d" (op_val) \
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: "cc", "memory"); \
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old_val; \
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})
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#endif /* CONFIG_HAVE_MARCH_Z196_FEATURES */
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static inline int atomic_read(const atomic_t *v)
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{
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int c;
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asm volatile(
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" l %0,%1\n"
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: "=d" (c) : "Q" (v->counter));
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return c;
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}
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static inline void atomic_set(atomic_t *v, int i)
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{
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asm volatile(
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" st %1,%0\n"
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: "=Q" (v->counter) : "d" (i));
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}
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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return __ATOMIC_LOOP(v, i, __ATOMIC_ADD, __ATOMIC_BARRIER) + i;
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}
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static inline void atomic_add(int i, atomic_t *v)
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{
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#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
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if (__builtin_constant_p(i) && (i > -129) && (i < 128)) {
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asm volatile(
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"asi %0,%1\n"
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: "+Q" (v->counter)
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: "i" (i)
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: "cc", "memory");
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return;
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}
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#endif
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__ATOMIC_LOOP(v, i, __ATOMIC_ADD, __ATOMIC_NO_BARRIER);
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}
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#define atomic_add_negative(_i, _v) (atomic_add_return(_i, _v) < 0)
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#define atomic_inc(_v) atomic_add(1, _v)
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#define atomic_inc_return(_v) atomic_add_return(1, _v)
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#define atomic_inc_and_test(_v) (atomic_add_return(1, _v) == 0)
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#define atomic_sub(_i, _v) atomic_add(-(int)(_i), _v)
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#define atomic_sub_return(_i, _v) atomic_add_return(-(int)(_i), _v)
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#define atomic_sub_and_test(_i, _v) (atomic_sub_return(_i, _v) == 0)
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#define atomic_dec(_v) atomic_sub(1, _v)
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#define atomic_dec_return(_v) atomic_sub_return(1, _v)
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#define atomic_dec_and_test(_v) (atomic_sub_return(1, _v) == 0)
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static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
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{
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__ATOMIC_LOOP(v, ~mask, __ATOMIC_AND, __ATOMIC_NO_BARRIER);
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}
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static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
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{
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__ATOMIC_LOOP(v, mask, __ATOMIC_OR, __ATOMIC_NO_BARRIER);
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}
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
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{
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asm volatile(
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" cs %0,%2,%1"
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: "+d" (old), "+Q" (v->counter)
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: "d" (new)
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: "cc", "memory");
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return old;
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}
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static inline int __atomic_add_unless(atomic_t *v, int a, int u)
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{
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int c, old;
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c = atomic_read(v);
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for (;;) {
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if (unlikely(c == u))
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break;
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old = atomic_cmpxchg(v, c, c + a);
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if (likely(old == c))
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break;
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c = old;
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}
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return c;
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}
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#undef __ATOMIC_LOOP
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#define ATOMIC64_INIT(i) { (i) }
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#ifdef CONFIG_64BIT
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#define __ATOMIC64_NO_BARRIER "\n"
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#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
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#define __ATOMIC64_OR "laog"
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#define __ATOMIC64_AND "lang"
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#define __ATOMIC64_ADD "laag"
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#define __ATOMIC64_BARRIER "bcr 14,0\n"
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#define __ATOMIC64_LOOP(ptr, op_val, op_string, __barrier) \
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({ \
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long long old_val; \
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\
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typecheck(atomic64_t *, ptr); \
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asm volatile( \
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__barrier \
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op_string " %0,%2,%1\n" \
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__barrier \
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: "=d" (old_val), "+Q" ((ptr)->counter) \
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: "d" (op_val) \
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: "cc", "memory"); \
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old_val; \
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})
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#else /* CONFIG_HAVE_MARCH_Z196_FEATURES */
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#define __ATOMIC64_OR "ogr"
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#define __ATOMIC64_AND "ngr"
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#define __ATOMIC64_ADD "agr"
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#define __ATOMIC64_BARRIER "\n"
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#define __ATOMIC64_LOOP(ptr, op_val, op_string, __barrier) \
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({ \
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long long old_val, new_val; \
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\
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typecheck(atomic64_t *, ptr); \
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asm volatile( \
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" lg %0,%2\n" \
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"0: lgr %1,%0\n" \
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op_string " %1,%3\n" \
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" csg %0,%1,%2\n" \
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" jl 0b" \
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: "=&d" (old_val), "=&d" (new_val), "+Q" ((ptr)->counter)\
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: "d" (op_val) \
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: "cc", "memory"); \
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old_val; \
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})
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#endif /* CONFIG_HAVE_MARCH_Z196_FEATURES */
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static inline long long atomic64_read(const atomic64_t *v)
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{
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long long c;
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asm volatile(
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" lg %0,%1\n"
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: "=d" (c) : "Q" (v->counter));
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return c;
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}
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static inline void atomic64_set(atomic64_t *v, long long i)
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{
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asm volatile(
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" stg %1,%0\n"
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: "=Q" (v->counter) : "d" (i));
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}
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static inline long long atomic64_add_return(long long i, atomic64_t *v)
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{
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return __ATOMIC64_LOOP(v, i, __ATOMIC64_ADD, __ATOMIC64_BARRIER) + i;
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}
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static inline void atomic64_add(long long i, atomic64_t *v)
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{
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#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
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if (__builtin_constant_p(i) && (i > -129) && (i < 128)) {
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asm volatile(
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"agsi %0,%1\n"
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: "+Q" (v->counter)
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: "i" (i)
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: "cc", "memory");
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return;
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}
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#endif
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__ATOMIC64_LOOP(v, i, __ATOMIC64_ADD, __ATOMIC64_NO_BARRIER);
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}
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static inline void atomic64_clear_mask(unsigned long mask, atomic64_t *v)
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{
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__ATOMIC64_LOOP(v, ~mask, __ATOMIC64_AND, __ATOMIC64_NO_BARRIER);
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}
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static inline void atomic64_set_mask(unsigned long mask, atomic64_t *v)
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{
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__ATOMIC64_LOOP(v, mask, __ATOMIC64_OR, __ATOMIC64_NO_BARRIER);
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}
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#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
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static inline long long atomic64_cmpxchg(atomic64_t *v,
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long long old, long long new)
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{
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asm volatile(
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" csg %0,%2,%1"
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: "+d" (old), "+Q" (v->counter)
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: "d" (new)
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: "cc", "memory");
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return old;
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}
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#undef __ATOMIC64_LOOP
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#else /* CONFIG_64BIT */
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typedef struct {
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long long counter;
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} atomic64_t;
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static inline long long atomic64_read(const atomic64_t *v)
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{
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register_pair rp;
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asm volatile(
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" lm %0,%N0,%1"
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: "=&d" (rp) : "Q" (v->counter) );
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return rp.pair;
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}
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static inline void atomic64_set(atomic64_t *v, long long i)
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{
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register_pair rp = {.pair = i};
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asm volatile(
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" stm %1,%N1,%0"
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: "=Q" (v->counter) : "d" (rp) );
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}
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static inline long long atomic64_xchg(atomic64_t *v, long long new)
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{
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register_pair rp_new = {.pair = new};
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register_pair rp_old;
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asm volatile(
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" lm %0,%N0,%1\n"
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"0: cds %0,%2,%1\n"
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" jl 0b\n"
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: "=&d" (rp_old), "+Q" (v->counter)
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: "d" (rp_new)
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: "cc");
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return rp_old.pair;
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}
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static inline long long atomic64_cmpxchg(atomic64_t *v,
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long long old, long long new)
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{
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register_pair rp_old = {.pair = old};
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register_pair rp_new = {.pair = new};
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asm volatile(
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" cds %0,%2,%1"
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: "+&d" (rp_old), "+Q" (v->counter)
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: "d" (rp_new)
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: "cc");
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return rp_old.pair;
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}
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static inline long long atomic64_add_return(long long i, atomic64_t *v)
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{
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long long old, new;
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do {
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old = atomic64_read(v);
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new = old + i;
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} while (atomic64_cmpxchg(v, old, new) != old);
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return new;
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}
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static inline void atomic64_set_mask(unsigned long long mask, atomic64_t *v)
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{
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long long old, new;
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do {
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old = atomic64_read(v);
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new = old | mask;
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} while (atomic64_cmpxchg(v, old, new) != old);
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}
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static inline void atomic64_clear_mask(unsigned long long mask, atomic64_t *v)
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{
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long long old, new;
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do {
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old = atomic64_read(v);
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new = old & mask;
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} while (atomic64_cmpxchg(v, old, new) != old);
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}
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static inline void atomic64_add(long long i, atomic64_t *v)
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{
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atomic64_add_return(i, v);
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}
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#endif /* CONFIG_64BIT */
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static inline int atomic64_add_unless(atomic64_t *v, long long i, long long u)
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{
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long long c, old;
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c = atomic64_read(v);
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for (;;) {
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if (unlikely(c == u))
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break;
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old = atomic64_cmpxchg(v, c, c + i);
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if (likely(old == c))
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break;
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c = old;
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}
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return c != u;
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}
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static inline long long atomic64_dec_if_positive(atomic64_t *v)
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{
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long long c, old, dec;
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c = atomic64_read(v);
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for (;;) {
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dec = c - 1;
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if (unlikely(dec < 0))
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break;
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old = atomic64_cmpxchg((v), c, dec);
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if (likely(old == c))
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break;
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c = old;
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}
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return dec;
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}
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#define atomic64_add_negative(_i, _v) (atomic64_add_return(_i, _v) < 0)
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#define atomic64_inc(_v) atomic64_add(1, _v)
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#define atomic64_inc_return(_v) atomic64_add_return(1, _v)
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#define atomic64_inc_and_test(_v) (atomic64_add_return(1, _v) == 0)
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#define atomic64_sub_return(_i, _v) atomic64_add_return(-(long long)(_i), _v)
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#define atomic64_sub(_i, _v) atomic64_add(-(long long)(_i), _v)
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#define atomic64_sub_and_test(_i, _v) (atomic64_sub_return(_i, _v) == 0)
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#define atomic64_dec(_v) atomic64_sub(1, _v)
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#define atomic64_dec_return(_v) atomic64_sub_return(1, _v)
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#define atomic64_dec_and_test(_v) (atomic64_sub_return(1, _v) == 0)
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#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
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#endif /* __ARCH_S390_ATOMIC__ */
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