forked from Minki/linux
0d92971dd6
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
209 lines
5.0 KiB
C
209 lines
5.0 KiB
C
#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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/* returns the size of fifo context */
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static int
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nouveau_fifo_ctx_size(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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if (dev_priv->chipset >= 0x40)
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return 128;
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else
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if (dev_priv->chipset >= 0x17)
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return 64;
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return 32;
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}
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static void
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nv04_instmem_determine_amount(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int i;
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/* Figure out how much instance memory we need */
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if (dev_priv->card_type >= NV_40) {
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/* We'll want more instance memory than this on some NV4x cards.
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* There's a 16MB aperture to play with that maps onto the end
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* of vram. For now, only reserve a small piece until we know
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* more about what each chipset requires.
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*/
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switch (dev_priv->chipset) {
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case 0x40:
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case 0x47:
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case 0x49:
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case 0x4b:
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dev_priv->ramin_rsvd_vram = (2 * 1024 * 1024);
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break;
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default:
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dev_priv->ramin_rsvd_vram = (1 * 1024 * 1024);
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break;
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}
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} else {
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/*XXX: what *are* the limits on <NV40 cards?
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*/
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dev_priv->ramin_rsvd_vram = (512 * 1024);
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}
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NV_DEBUG(dev, "RAMIN size: %dKiB\n", dev_priv->ramin_rsvd_vram >> 10);
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/* Clear all of it, except the BIOS image that's in the first 64KiB */
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dev_priv->engine.instmem.prepare_access(dev, true);
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for (i = 64 * 1024; i < dev_priv->ramin_rsvd_vram; i += 4)
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nv_wi32(dev, i, 0x00000000);
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dev_priv->engine.instmem.finish_access(dev);
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}
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static void
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nv04_instmem_configure_fixed_tables(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_engine *engine = &dev_priv->engine;
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/* FIFO hash table (RAMHT)
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* use 4k hash table at RAMIN+0x10000
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* TODO: extend the hash table
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*/
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dev_priv->ramht_offset = 0x10000;
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dev_priv->ramht_bits = 9;
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dev_priv->ramht_size = (1 << dev_priv->ramht_bits); /* nr entries */
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dev_priv->ramht_size *= 8; /* 2 32-bit values per entry in RAMHT */
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NV_DEBUG(dev, "RAMHT offset=0x%x, size=%d\n", dev_priv->ramht_offset,
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dev_priv->ramht_size);
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/* FIFO runout table (RAMRO) - 512k at 0x11200 */
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dev_priv->ramro_offset = 0x11200;
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dev_priv->ramro_size = 512;
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NV_DEBUG(dev, "RAMRO offset=0x%x, size=%d\n", dev_priv->ramro_offset,
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dev_priv->ramro_size);
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/* FIFO context table (RAMFC)
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* NV40 : Not sure exactly how to position RAMFC on some cards,
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* 0x30002 seems to position it at RAMIN+0x20000 on these
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* cards. RAMFC is 4kb (32 fifos, 128byte entries).
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* Others: Position RAMFC at RAMIN+0x11400
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*/
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dev_priv->ramfc_size = engine->fifo.channels *
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nouveau_fifo_ctx_size(dev);
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switch (dev_priv->card_type) {
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case NV_40:
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dev_priv->ramfc_offset = 0x20000;
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break;
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case NV_30:
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case NV_20:
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case NV_10:
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case NV_04:
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default:
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dev_priv->ramfc_offset = 0x11400;
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break;
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}
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NV_DEBUG(dev, "RAMFC offset=0x%x, size=%d\n", dev_priv->ramfc_offset,
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dev_priv->ramfc_size);
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}
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int nv04_instmem_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t offset;
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int ret = 0;
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nv04_instmem_determine_amount(dev);
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nv04_instmem_configure_fixed_tables(dev);
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/* Create a heap to manage RAMIN allocations, we don't allocate
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* the space that was reserved for RAMHT/FC/RO.
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*/
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offset = dev_priv->ramfc_offset + dev_priv->ramfc_size;
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/* It appears RAMRO (or something?) is controlled by 0x2220/0x2230
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* on certain NV4x chipsets as well as RAMFC. When 0x2230 == 0
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* ("new style" control) the upper 16-bits of 0x2220 points at this
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* other mysterious table that's clobbering important things.
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*
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* We're now pointing this at RAMIN+0x30000 to avoid RAMFC getting
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* smashed to pieces on us, so reserve 0x30000-0x40000 too..
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*/
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if (dev_priv->card_type >= NV_40) {
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if (offset < 0x40000)
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offset = 0x40000;
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}
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ret = nouveau_mem_init_heap(&dev_priv->ramin_heap,
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offset, dev_priv->ramin_rsvd_vram - offset);
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if (ret) {
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dev_priv->ramin_heap = NULL;
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NV_ERROR(dev, "Failed to init RAMIN heap\n");
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}
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return ret;
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}
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void
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nv04_instmem_takedown(struct drm_device *dev)
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{
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}
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int
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nv04_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, uint32_t *sz)
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{
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if (gpuobj->im_backing)
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return -EINVAL;
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return 0;
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}
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void
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nv04_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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if (gpuobj && gpuobj->im_backing) {
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if (gpuobj->im_bound)
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dev_priv->engine.instmem.unbind(dev, gpuobj);
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gpuobj->im_backing = NULL;
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}
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}
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int
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nv04_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
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{
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if (!gpuobj->im_pramin || gpuobj->im_bound)
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return -EINVAL;
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gpuobj->im_bound = 1;
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return 0;
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}
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int
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nv04_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
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{
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if (gpuobj->im_bound == 0)
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return -EINVAL;
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gpuobj->im_bound = 0;
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return 0;
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}
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void
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nv04_instmem_prepare_access(struct drm_device *dev, bool write)
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{
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}
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void
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nv04_instmem_finish_access(struct drm_device *dev)
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{
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}
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int
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nv04_instmem_suspend(struct drm_device *dev)
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{
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return 0;
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}
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void
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nv04_instmem_resume(struct drm_device *dev)
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{
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}
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