forked from Minki/linux
2c25291762
* Convert to named i2c-gpio bindings Geert Uytterhoeven says "Commits7d29f509d2("dt-bindings: i2c: i2c-gpio: Add support for named gpios") and05c7477885("i2c: gpio: Add support for named gpios in DT") introduced named i2c-gpio DT bindings, and deprecated the more error-prone unnamed variant. This patch series switches all Renesas boards to the new bindings, and adds the missing GPIO_OPEN_DRAIN I/O flags, which were implicitly assumed before..." ... Note that after this series is applied, the i2c-gpio buses are no longer detected when booting new DTBs on old (v4.14 and older) kernels, which should not be an issue. Booting old DTBs on new kernels is not affected." * Update DTS for CMT DT binding rework Geert Uytterhoeven says "This patch series updates the CMT device nodes in the various Renesas DTS files sh_cmt clocksource driver for the recent DT binding rework that was merged in v4.14-rc1 and v4.15-rc1..." * Add SMP support to r8a7794 (R-Car E2) SoC Sergei Shtylyov says "Add the device tree node for the Advanced Power Management Unit (APMU). Use the "enable-method" prop to point out that the APMU should be used for the SMP support." * Correct primary compatible value for eeprom on r7s72100 (RZ/A1H) genmai and r8a7791 (R-Car M2-W) koelsh boards Geert Uytterhoeven says "The Renesas part numbers of the two-wire serial interface EEPROMs do not follow the 24Cxx pattern, but the R1EX24xxx pattern. Hence change the primary compatible values to the appropriate variant of "renesas,r1ex24xxx", like is already done on Gose."" * Move cec_clock to root node on r8a7791 (R-Car M2-W) koelsh board r8a7791 (R-Car M2-W) koelsh board * Use R-Car SDHI and Ether Gen1 and 2 fallback compat strings Use recently posted R-Car SDHI and Ether Gen 1 and 2 fallback compat strings in the DT of Renesas ARM based SoCs. * Add IIC cores to dtsi of r8a7745 (RZ/G1E) SoC * Rework DT architecture for r8a7745 (RZ/G1E) iW-RainboW-G22D development platform and add serial support. Fabrizio Castro says "... define a new DT architecture for the iW-RainboW-G22D SODIMM Development Platform to include the configuration with the HDMI daughter board and to define the serial interfaces." * Add USB function support to r8a7745 (RZ/G1E) iW-RainboW-G22D development platform * Add PCIEC and ttySC3 support to r8a7743 (RZ/G1M) iW-RainboW-G20M-Qseven SoM * Add VIN support to r8a7743 (RZ/G1M) and r8a7745 (RZ/G1E) SoCs * Add CAN and HDMI support to r8a7743 (RZ/G1M) iW-RainboW-G20D-Qseven and r8a7745 (RZ/G1E) iW-RainboW-G22D development platforms -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAlonxA0ACgkQ189kaWo3 T76EtA//RMlwBDrH9XbrrPEtMePSTsXisKQPooYV/NOO1RcvAZjSILtzmdzpwipr pm8Ogdou6E3dX0i0+OnZRw+62apaK0xt0tuRf4ayxfKCWhqWnTpFOf8icNyXbQ0w fr0Q//lPdAEW5+qD15dAtbASqQqUntgsCldQHXS8+KlLEs9BHfZxU9Myyqr+pJHH +7C6Jwy68bSvhIxtbJRNbkA4jj464Tcy0OsDJdNktEduGPel7llew+Zv3WI/dpoL Q0BMbkpTUctK6VuYvJZt7RlKwkOpW7xlePi4SP87AnUYnYHhYQAA5Lz+uJIv4EVq 0SQadPbXnDl9BtTrKXPmWLIYG+OTh4mx1Gf49dvmh2737NydbSzbam3DprgJW6+T lsyAMvU/LWgdRv8wuZfS6EJ63UjPRqq0siZdWYQX7vEXveIgjVrY3yF6av8RJJhy YRnvKx2oASo/+uskBs8EY73yIPPiQO3KBdCTRwOOtllQo7lTXaM6s2pmNWfkJjm8 xXBo2V6/qLEwBnT4MEPGEM+uj4kiRKtWDwmVtb+YqDEH3l4ztyVfjOgw+DZj5XnC jo6253AIHAY90XXapKqgXJ20+Xb4JfmPYPsU/t2sGrWKNA/IahPxI3QbXDpdgCH0 alAiohPojdbR+zOynPKNTZC5/DwYOGcKfsyh5ClXCAmY7yFhGtM= =Yk5x -----END PGP SIGNATURE----- Merge tag 'renesas-dt-for-v4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Pull "Renesas ARM Based SoC DT Updates for v4.16" from Simon Horman: * Convert to named i2c-gpio bindings Geert Uytterhoeven says "Commits7d29f509d2("dt-bindings: i2c: i2c-gpio: Add support for named gpios") and05c7477885("i2c: gpio: Add support for named gpios in DT") introduced named i2c-gpio DT bindings, and deprecated the more error-prone unnamed variant. This patch series switches all Renesas boards to the new bindings, and adds the missing GPIO_OPEN_DRAIN I/O flags, which were implicitly assumed before..." ... Note that after this series is applied, the i2c-gpio buses are no longer detected when booting new DTBs on old (v4.14 and older) kernels, which should not be an issue. Booting old DTBs on new kernels is not affected." * Update DTS for CMT DT binding rework Geert Uytterhoeven says "This patch series updates the CMT device nodes in the various Renesas DTS files sh_cmt clocksource driver for the recent DT binding rework that was merged in v4.14-rc1 and v4.15-rc1..." * Add SMP support to r8a7794 (R-Car E2) SoC Sergei Shtylyov says "Add the device tree node for the Advanced Power Management Unit (APMU). Use the "enable-method" prop to point out that the APMU should be used for the SMP support." * Correct primary compatible value for eeprom on r7s72100 (RZ/A1H) genmai and r8a7791 (R-Car M2-W) koelsh boards Geert Uytterhoeven says "The Renesas part numbers of the two-wire serial interface EEPROMs do not follow the 24Cxx pattern, but the R1EX24xxx pattern. Hence change the primary compatible values to the appropriate variant of "renesas,r1ex24xxx", like is already done on Gose."" * Move cec_clock to root node on r8a7791 (R-Car M2-W) koelsh board r8a7791 (R-Car M2-W) koelsh board * Use R-Car SDHI and Ether Gen1 and 2 fallback compat strings Use recently posted R-Car SDHI and Ether Gen 1 and 2 fallback compat strings in the DT of Renesas ARM based SoCs. * Add IIC cores to dtsi of r8a7745 (RZ/G1E) SoC * Rework DT architecture for r8a7745 (RZ/G1E) iW-RainboW-G22D development platform and add serial support. Fabrizio Castro says "... define a new DT architecture for the iW-RainboW-G22D SODIMM Development Platform to include the configuration with the HDMI daughter board and to define the serial interfaces." * Add USB function support to r8a7745 (RZ/G1E) iW-RainboW-G22D development platform * Add PCIEC and ttySC3 support to r8a7743 (RZ/G1M) iW-RainboW-G20M-Qseven SoM * Add VIN support to r8a7743 (RZ/G1M) and r8a7745 (RZ/G1E) SoCs * Add CAN and HDMI support to r8a7743 (RZ/G1M) iW-RainboW-G20D-Qseven and r8a7745 (RZ/G1E) iW-RainboW-G22D development platforms * tag 'renesas-dt-for-v4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (61 commits) ARM: dts: alt: Convert to named i2c-gpio bindings ARM: dts: koelsch: Convert to named i2c-gpio bindings ARM: dts: lager: Convert to named i2c-gpio bindings ARM: dts: armadillo800eva: Convert to named i2c-gpio bindings ARM: dts: sh73a0: Remove CMT renesas,channels-mask ARM: dts: r8a7794: Remove CMT renesas,channels-mask ARM: dts: r8a7793: Remove CMT renesas,channels-mask ARM: dts: r8a7791: Remove CMT renesas,channels-mask ARM: dts: r8a7790: Remove CMT renesas,channels-mask ARM: dts: r8a7740: Remove CMT renesas,channels-mask ARM: dts: r8a73a4: Remove CMT renesas,channels-mask ARM: dts: r8a7794: Update CMT compat strings ARM: dts: r8a7793: Update CMT compat strings ARM: dts: r8a7791: Update CMT compat strings ARM: dts: r8a7790: Update CMT compat strings ARM: dts: r8a73a4: Update CMT compat string ARM: dts: r8a7794: Add SMP support ARM: dts: genmai: Correct primary compatible value for eeprom ARM: dts: koelsch: Correct primary compatible value for eeprom ARM: dts: r8a7745: add VIN dt support ...
861 lines
24 KiB
Plaintext
861 lines
24 KiB
Plaintext
/*
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* Device Tree Source for the r8a7792 SoC
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*
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* Copyright (C) 2016 Cogent Embedded Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a7792-sysc.h>
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/ {
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compatible = "renesas,r8a7792";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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spi0 = &qspi;
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spi1 = &msiof0;
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spi2 = &msiof1;
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vin0 = &vin0;
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vin1 = &vin1;
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vin2 = &vin2;
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vin3 = &vin3;
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vin4 = &vin4;
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vin5 = &vin5;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "renesas,apmu";
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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clock-frequency = <1000000000>;
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clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
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power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
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next-level-cache = <&L2_CA15>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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clock-frequency = <1000000000>;
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clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
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power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
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next-level-cache = <&L2_CA15>;
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};
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L2_CA15: cache-controller-0 {
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compatible = "cache";
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cache-unified;
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cache-level = <2>;
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power-domains = <&sysc R8A7792_PD_CA15_SCU>;
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};
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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apmu@e6152000 {
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compatible = "renesas,r8a7792-apmu", "renesas,apmu";
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reg = <0 0xe6152000 0 0x188>;
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cpus = <&cpu0 &cpu1>;
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};
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gic: interrupt-controller@f1001000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0 0xf1001000 0 0x1000>,
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<0 0xf1002000 0 0x2000>,
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<0 0xf1004000 0 0x2000>,
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<0 0xf1006000 0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&cpg CPG_MOD 408>;
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clock-names = "clk";
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 408>;
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};
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irqc: interrupt-controller@e61c0000 {
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compatible = "renesas,irqc-r8a7792", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 407>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 407>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a7792-rst";
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reg = <0 0xe6160000 0 0x0100>;
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};
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prr: chipid@ff000044 {
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compatible = "renesas,prr";
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reg = <0 0xff000044 0 4>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a7792-sysc";
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reg = <0 0xe6180000 0 0x0200>;
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#power-domain-cells = <1>;
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};
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pfc: pin-controller@e6060000 {
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compatible = "renesas,pfc-r8a7792";
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reg = <0 0xe6060000 0 0x144>;
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};
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gpio0: gpio@e6050000 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,rcar-gen2-gpio";
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reg = <0 0xe6050000 0 0x50>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 0 29>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 912>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 912>;
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};
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gpio1: gpio@e6051000 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,rcar-gen2-gpio";
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reg = <0 0xe6051000 0 0x50>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 23>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 911>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 911>;
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};
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gpio2: gpio@e6052000 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,rcar-gen2-gpio";
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reg = <0 0xe6052000 0 0x50>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 64 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 910>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 910>;
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};
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gpio3: gpio@e6053000 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,rcar-gen2-gpio";
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reg = <0 0xe6053000 0 0x50>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 96 28>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 909>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 909>;
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};
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gpio4: gpio@e6054000 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,rcar-gen2-gpio";
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reg = <0 0xe6054000 0 0x50>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 128 17>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 908>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 908>;
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};
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gpio5: gpio@e6055000 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,rcar-gen2-gpio";
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reg = <0 0xe6055000 0 0x50>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 160 17>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 907>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 907>;
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};
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gpio6: gpio@e6055100 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,rcar-gen2-gpio";
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reg = <0 0xe6055100 0 0x50>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 192 17>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 905>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 905>;
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};
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gpio7: gpio@e6055200 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,rcar-gen2-gpio";
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reg = <0 0xe6055200 0 0x50>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 224 17>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 904>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 904>;
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};
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gpio8: gpio@e6055300 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,rcar-gen2-gpio";
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reg = <0 0xe6055300 0 0x50>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 256 17>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 921>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 921>;
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};
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gpio9: gpio@e6055400 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,rcar-gen2-gpio";
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reg = <0 0xe6055400 0 0x50>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 288 17>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 919>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 919>;
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};
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gpio10: gpio@e6055500 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,rcar-gen2-gpio";
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reg = <0 0xe6055500 0 0x50>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 320 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 914>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 914>;
|
|
};
|
|
|
|
gpio11: gpio@e6055600 {
|
|
compatible = "renesas,gpio-r8a7792",
|
|
"renesas,rcar-gen2-gpio";
|
|
reg = <0 0xe6055600 0 0x50>;
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
gpio-ranges = <&pfc 0 352 30>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
clocks = <&cpg CPG_MOD 913>;
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 913>;
|
|
};
|
|
|
|
dmac0: dma-controller@e6700000 {
|
|
compatible = "renesas,dmac-r8a7792",
|
|
"renesas,rcar-dmac";
|
|
reg = <0 0xe6700000 0 0x20000>;
|
|
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14";
|
|
clocks = <&cpg CPG_MOD 219>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 219>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <15>;
|
|
};
|
|
|
|
dmac1: dma-controller@e6720000 {
|
|
compatible = "renesas,dmac-r8a7792",
|
|
"renesas,rcar-dmac";
|
|
reg = <0 0xe6720000 0 0x20000>;
|
|
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14";
|
|
clocks = <&cpg CPG_MOD 218>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 218>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <15>;
|
|
};
|
|
|
|
scif0: serial@e6e60000 {
|
|
compatible = "renesas,scif-r8a7792",
|
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
|
reg = <0 0xe6e60000 0 64>;
|
|
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 721>,
|
|
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
|
|
<&dmac1 0x29>, <&dmac1 0x2a>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 721>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif1: serial@e6e68000 {
|
|
compatible = "renesas,scif-r8a7792",
|
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
|
reg = <0 0xe6e68000 0 64>;
|
|
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 720>,
|
|
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
|
|
<&dmac1 0x2d>, <&dmac1 0x2e>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 720>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif2: serial@e6e58000 {
|
|
compatible = "renesas,scif-r8a7792",
|
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
|
reg = <0 0xe6e58000 0 64>;
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 719>,
|
|
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
|
|
<&dmac1 0x2b>, <&dmac1 0x2c>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 719>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif3: serial@e6ea8000 {
|
|
compatible = "renesas,scif-r8a7792",
|
|
"renesas,rcar-gen2-scif", "renesas,scif";
|
|
reg = <0 0xe6ea8000 0 64>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 718>,
|
|
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
|
|
<&dmac1 0x2f>, <&dmac1 0x30>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 718>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif0: serial@e62c0000 {
|
|
compatible = "renesas,hscif-r8a7792",
|
|
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
|
reg = <0 0xe62c0000 0 96>;
|
|
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 717>,
|
|
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
|
|
<&dmac1 0x39>, <&dmac1 0x3a>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 717>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif1: serial@e62c8000 {
|
|
compatible = "renesas,hscif-r8a7792",
|
|
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
|
reg = <0 0xe62c8000 0 96>;
|
|
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 716>,
|
|
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
|
|
<&dmac1 0x4d>, <&dmac1 0x4e>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 716>;
|
|
status = "disabled";
|
|
};
|
|
|
|
icram0: sram@e63a0000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0 0xe63a0000 0 0x12000>;
|
|
};
|
|
|
|
icram1: sram@e63c0000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0 0xe63c0000 0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0xe63c0000 0x1000>;
|
|
|
|
smp-sram@0 {
|
|
compatible = "renesas,smp-sram";
|
|
reg = <0 0x10>;
|
|
};
|
|
};
|
|
|
|
sdhi0: sd@ee100000 {
|
|
compatible = "renesas,sdhi-r8a7792",
|
|
"renesas,rcar-gen2-sdhi";
|
|
reg = <0 0xee100000 0 0x328>;
|
|
interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
|
|
<&dmac1 0xcd>, <&dmac1 0xce>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
clocks = <&cpg CPG_MOD 314>;
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 314>;
|
|
status = "disabled";
|
|
};
|
|
|
|
jpu: jpeg-codec@fe980000 {
|
|
compatible = "renesas,jpu-r8a7792",
|
|
"renesas,rcar-gen2-jpu";
|
|
reg = <0 0xfe980000 0 0x10300>;
|
|
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 106>;
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 106>;
|
|
};
|
|
|
|
avb: ethernet@e6800000 {
|
|
compatible = "renesas,etheravb-r8a7792",
|
|
"renesas,etheravb-rcar-gen2";
|
|
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
|
|
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 812>;
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 812>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* I2C doesn't need pinmux */
|
|
i2c0: i2c@e6508000 {
|
|
compatible = "renesas,i2c-r8a7792",
|
|
"renesas,rcar-gen2-i2c";
|
|
reg = <0 0xe6508000 0 0x40>;
|
|
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 931>;
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 931>;
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@e6518000 {
|
|
compatible = "renesas,i2c-r8a7792",
|
|
"renesas,rcar-gen2-i2c";
|
|
reg = <0 0xe6518000 0 0x40>;
|
|
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 930>;
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 930>;
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@e6530000 {
|
|
compatible = "renesas,i2c-r8a7792",
|
|
"renesas,rcar-gen2-i2c";
|
|
reg = <0 0xe6530000 0 0x40>;
|
|
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 929>;
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 929>;
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@e6540000 {
|
|
compatible = "renesas,i2c-r8a7792",
|
|
"renesas,rcar-gen2-i2c";
|
|
reg = <0 0xe6540000 0 0x40>;
|
|
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 928>;
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 928>;
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@e6520000 {
|
|
compatible = "renesas,i2c-r8a7792",
|
|
"renesas,rcar-gen2-i2c";
|
|
reg = <0 0xe6520000 0 0x40>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 927>;
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 927>;
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@e6528000 {
|
|
compatible = "renesas,i2c-r8a7792",
|
|
"renesas,rcar-gen2-i2c";
|
|
reg = <0 0xe6528000 0 0x40>;
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 925>;
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 925>;
|
|
i2c-scl-internal-delay-ns = <110>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qspi: spi@e6b10000 {
|
|
compatible = "renesas,qspi-r8a7792", "renesas,qspi";
|
|
reg = <0 0xe6b10000 0 0x2c>;
|
|
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 917>;
|
|
dmas = <&dmac0 0x17>, <&dmac0 0x18>,
|
|
<&dmac1 0x17>, <&dmac1 0x18>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 917>;
|
|
num-cs = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof0: spi@e6e20000 {
|
|
compatible = "renesas,msiof-r8a7792",
|
|
"renesas,rcar-gen2-msiof";
|
|
reg = <0 0xe6e20000 0 0x0064>;
|
|
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 000>;
|
|
dmas = <&dmac0 0x51>, <&dmac0 0x52>,
|
|
<&dmac1 0x51>, <&dmac1 0x52>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof1: spi@e6e10000 {
|
|
compatible = "renesas,msiof-r8a7792",
|
|
"renesas,rcar-gen2-msiof";
|
|
reg = <0 0xe6e10000 0 0x0064>;
|
|
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 208>;
|
|
dmas = <&dmac0 0x55>, <&dmac0 0x56>,
|
|
<&dmac1 0x55>, <&dmac1 0x56>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 208>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
du: display@feb00000 {
|
|
compatible = "renesas,du-r8a7792";
|
|
reg = <0 0xfeb00000 0 0x40000>;
|
|
reg-names = "du";
|
|
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 724>,
|
|
<&cpg CPG_MOD 723>;
|
|
clock-names = "du.0", "du.1";
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
du_out_rgb0: endpoint {
|
|
};
|
|
};
|
|
port@1 {
|
|
reg = <1>;
|
|
du_out_rgb1: endpoint {
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
can0: can@e6e80000 {
|
|
compatible = "renesas,can-r8a7792",
|
|
"renesas,rcar-gen2-can";
|
|
reg = <0 0xe6e80000 0 0x1000>;
|
|
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 916>,
|
|
<&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
|
|
clock-names = "clkp1", "clkp2", "can_clk";
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 916>;
|
|
status = "disabled";
|
|
};
|
|
|
|
can1: can@e6e88000 {
|
|
compatible = "renesas,can-r8a7792",
|
|
"renesas,rcar-gen2-can";
|
|
reg = <0 0xe6e88000 0 0x1000>;
|
|
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 915>,
|
|
<&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
|
|
clock-names = "clkp1", "clkp2", "can_clk";
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 915>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vin0: video@e6ef0000 {
|
|
compatible = "renesas,vin-r8a7792",
|
|
"renesas,rcar-gen2-vin";
|
|
reg = <0 0xe6ef0000 0 0x1000>;
|
|
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 811>;
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 811>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vin1: video@e6ef1000 {
|
|
compatible = "renesas,vin-r8a7792",
|
|
"renesas,rcar-gen2-vin";
|
|
reg = <0 0xe6ef1000 0 0x1000>;
|
|
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 810>;
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 810>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vin2: video@e6ef2000 {
|
|
compatible = "renesas,vin-r8a7792",
|
|
"renesas,rcar-gen2-vin";
|
|
reg = <0 0xe6ef2000 0 0x1000>;
|
|
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 809>;
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 809>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vin3: video@e6ef3000 {
|
|
compatible = "renesas,vin-r8a7792",
|
|
"renesas,rcar-gen2-vin";
|
|
reg = <0 0xe6ef3000 0 0x1000>;
|
|
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 808>;
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 808>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vin4: video@e6ef4000 {
|
|
compatible = "renesas,vin-r8a7792",
|
|
"renesas,rcar-gen2-vin";
|
|
reg = <0 0xe6ef4000 0 0x1000>;
|
|
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 805>;
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 805>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vin5: video@e6ef5000 {
|
|
compatible = "renesas,vin-r8a7792",
|
|
"renesas,rcar-gen2-vin";
|
|
reg = <0 0xe6ef5000 0 0x1000>;
|
|
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 804>;
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 804>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vsp@fe928000 {
|
|
compatible = "renesas,vsp1";
|
|
reg = <0 0xfe928000 0 0x8000>;
|
|
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 131>;
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 131>;
|
|
};
|
|
|
|
vsp@fe930000 {
|
|
compatible = "renesas,vsp1";
|
|
reg = <0 0xfe930000 0 0x8000>;
|
|
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 128>;
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 128>;
|
|
};
|
|
|
|
vsp@fe938000 {
|
|
compatible = "renesas,vsp1";
|
|
reg = <0 0xfe938000 0 0x8000>;
|
|
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 127>;
|
|
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
|
resets = <&cpg 127>;
|
|
};
|
|
|
|
cpg: clock-controller@e6150000 {
|
|
compatible = "renesas,r8a7792-cpg-mssr";
|
|
reg = <0 0xe6150000 0 0x1000>;
|
|
clocks = <&extal_clk>;
|
|
clock-names = "extal";
|
|
#clock-cells = <2>;
|
|
#power-domain-cells = <0>;
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
|
|
/* External root clock */
|
|
extal_clk: extal {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
/* This value must be overridden by the board. */
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
/* External SCIF clock */
|
|
scif_clk: scif {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
/* This value must be overridden by the board. */
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
/* External CAN clock */
|
|
can_clk: can {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
/* This value must be overridden by the board. */
|
|
clock-frequency = <0>;
|
|
};
|
|
};
|