forked from Minki/linux
bc3d3447b6
Currently if the Foundation model is running ARM Trusted Firmware then the kernel, which is configured to use spin tables, cannot start secondary processors or "power off" the simulation. After adding a couple of labels to the include file and splitting out the spin-table configuration into a header, we add a couple of new headers together with two new DTs (GICv2 + PSCI and GICv3 + PSCI). The new GICv3+PSCI DT has been boot tested, the remaining three (two of which existed prior to this patch) have been "tested" by decompiling the blobs and comparing them against a reference. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
29 lines
570 B
Plaintext
29 lines
570 B
Plaintext
/*
|
|
* ARM Ltd.
|
|
*
|
|
* ARMv8 Foundation model DTS (GICv3 configuration)
|
|
*/
|
|
|
|
/ {
|
|
gic: interrupt-controller@2f000000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
interrupt-controller;
|
|
reg = <0x0 0x2f000000 0x0 0x10000>,
|
|
<0x0 0x2f100000 0x0 0x200000>,
|
|
<0x0 0x2c000000 0x0 0x2000>,
|
|
<0x0 0x2c010000 0x0 0x2000>,
|
|
<0x0 0x2c02f000 0x0 0x2000>;
|
|
interrupts = <1 9 4>;
|
|
|
|
its: its@2f020000 {
|
|
compatible = "arm,gic-v3-its";
|
|
msi-controller;
|
|
reg = <0x0 0x2f020000 0x0 0x20000>;
|
|
};
|
|
};
|
|
};
|