linux/drivers/clk/rockchip
Douglas Anderson 2bbfe00147 clk: rockchip: Fix PLL bandwidth
In the TRM we see that BWADJ is "a 12-bit bus that selects the values
1-4096 for the bandwidth divider (NB)":
 NB = BWADJ[11:0] + 1
The recommended setting of NB: NB = NF / 2.

So:
  NB = NF / 2
  BWADJ[11:0] + 1 = NF / 2
  BWADJ[11:0] = NF / 2 - 1

Right now, we have:

{                                               \
        .rate   = _rate##U,                     \
        .nr = _nr,                              \
        .nf = _nf,                              \
        .no = _no,                              \
        .bwadj = (_nf >> 1),                    \
}

That means we set bwadj to NF / 2, not NF / 2 - 1

All of this is a bit confusing because we specify "NR" (the 1-based
value), "NF" (the 1-based value), "NO" (the 1-based value), but
"BWADJ" (the 0-based value) instead of "NB" (the 1-based value).

Let's change to working with "NB" and fix the off by one error.  This
may affect PLL jitter in a small way (hopefully for the better).

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:59:12 -07:00
..
clk-cpu.c clk: rockchip: Properly include clk.h 2015-07-20 11:11:10 -07:00
clk-inverter.c clk: rockchip: add support for phase inverters 2015-07-06 15:04:40 -07:00
clk-mmc-phase.c Merge branch 'cleanup-clk-h-includes' into clk-next 2015-07-28 11:59:09 -07:00
clk-pll.c clk: rockchip: Fix PLL bandwidth 2015-07-28 11:59:12 -07:00
clk-rk3188.c clk: rockchip: Fix PLL bandwidth 2015-07-28 11:59:12 -07:00
clk-rk3288.c clk: rockchip: Fix PLL bandwidth 2015-07-28 11:59:12 -07:00
clk-rk3368.c clk: rockchip: add rk3368 clock controller 2015-07-06 15:09:22 -07:00
clk-rockchip.c clk: rockchip: fix function type for CLK_OF_DECLARE 2014-05-20 14:25:22 -05:00
clk.c clk: rockchip: add support for phase inverters 2015-07-06 15:04:40 -07:00
clk.h clk: rockchip: Fix PLL bandwidth 2015-07-28 11:59:12 -07:00
Makefile clk: rockchip: add rk3368 clock controller 2015-07-06 15:09:22 -07:00
softrst.c clk: rockchip: add reset controller 2014-07-13 12:17:07 -07:00