2bab3cf910
L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon SoC. This patch adds support for HHA PMU driver, Each HHA has own control, counter and interrupt registers and is an separate PMU. For each HHA PMU, it has 16-programable counters and each counter is free-running. Interrupt is supported to handle counter (48-bits) overflow. Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> Signed-off-by: Anurup M <anurup.m@huawei.com> Signed-off-by: Will Deacon <will.deacon@arm.com> |
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| .. | ||
| hisilicon | ||
| arm_pmu_acpi.c | ||
| arm_pmu_platform.c | ||
| arm_pmu.c | ||
| arm_spe_pmu.c | ||
| Kconfig | ||
| Makefile | ||
| qcom_l2_pmu.c | ||
| qcom_l3_pmu.c | ||
| xgene_pmu.c | ||