Andy Shevchenko 2b8f8eddaf x86/platform/intel/pmc_atom: Add Cherrytrail PMC interface ... The patch adds CHT PMC interface. This exposes all the South IP device power states and S0ix states for CHT. The bit map of FUNC_DIS and D3_STS_0 registers for SoCs are consistent. The D3_STS_1 and FUNC_DIS_2 registers, however, are not aligned. This is fixed by splitting a common mapping on per register basis. (Originally based on code from Kumar P Mahesh.) Originally-from: Kumar P Mahesh <mahesh.kumar.p@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Aubrey Li <aubrey.li@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1436192944-56496-5-git-send-email-andriy.shevchenko@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>		2015-07-06 18:39:38 +02:00
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asm	x86/platform/intel/pmc_atom: Add Cherrytrail PMC interface	2015-07-06 18:39:38 +02:00
uapi/asm	kvm: add hyper-v crash msrs values	2015-07-03 18:55:20 +02:00