forked from Minki/linux
e96e2f1480
Patch against 2.6.12 to unhide SMBus on Toshiba Centrino laptops using Intel 82855PM chipset. Tested on Toshiba Tecra M2. Signed-off-by: Daniele Gaffuri <d.gaffuri@reply.it> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
1367 lines
45 KiB
C
1367 lines
45 KiB
C
/*
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* This file contains work-arounds for many known PCI hardware
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* bugs. Devices present only on certain architectures (host
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* bridges et cetera) should be handled in arch-specific code.
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*
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* Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
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*
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* Copyright (c) 1999 Martin Mares <mj@ucw.cz>
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*
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* The bridge optimization stuff has been removed. If you really
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* have a silly BIOS which is unable to set your host bridge right,
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* use the PowerTweak utility (see http://powertweak.sourceforge.net).
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*/
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/acpi.h>
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#include "pci.h"
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/* Deal with broken BIOS'es that neglect to enable passive release,
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which can cause problems in combination with the 82441FX/PPro MTRRs */
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static void __devinit quirk_passive_release(struct pci_dev *dev)
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{
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struct pci_dev *d = NULL;
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unsigned char dlc;
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/* We have to make sure a particular bit is set in the PIIX3
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ISA bridge, so we have to go out and find it. */
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while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
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pci_read_config_byte(d, 0x82, &dlc);
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if (!(dlc & 1<<1)) {
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printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
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dlc |= 1<<1;
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pci_write_config_byte(d, 0x82, dlc);
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}
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}
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
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/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
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but VIA don't answer queries. If you happen to have good contacts at VIA
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ask them for me please -- Alan
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This appears to be BIOS not version dependent. So presumably there is a
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chipset level fix */
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int isa_dma_bridge_buggy; /* Exported */
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static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
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{
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if (!isa_dma_bridge_buggy) {
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isa_dma_bridge_buggy=1;
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printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
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}
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}
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/*
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* Its not totally clear which chipsets are the problematic ones
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* We know 82C586 and 82C596 variants are affected.
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*/
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
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int pci_pci_problems;
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/*
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* Chipsets where PCI->PCI transfers vanish or hang
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*/
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static void __devinit quirk_nopcipci(struct pci_dev *dev)
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{
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if ((pci_pci_problems & PCIPCI_FAIL)==0) {
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printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
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pci_pci_problems |= PCIPCI_FAIL;
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}
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
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/*
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* Triton requires workarounds to be used by the drivers
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*/
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static void __devinit quirk_triton(struct pci_dev *dev)
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{
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if ((pci_pci_problems&PCIPCI_TRITON)==0) {
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printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
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pci_pci_problems |= PCIPCI_TRITON;
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}
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
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/*
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* VIA Apollo KT133 needs PCI latency patch
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* Made according to a windows driver based patch by George E. Breese
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* see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
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* Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
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* the info on which Mr Breese based his work.
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*
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* Updated based on further information from the site and also on
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* information provided by VIA
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*/
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static void __devinit quirk_vialatency(struct pci_dev *dev)
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{
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struct pci_dev *p;
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u8 rev;
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u8 busarb;
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/* Ok we have a potential problem chipset here. Now see if we have
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a buggy southbridge */
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p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
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if (p!=NULL) {
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pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
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/* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
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/* Check for buggy part revisions */
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if (rev < 0x40 || rev > 0x42)
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goto exit;
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} else {
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p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
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if (p==NULL) /* No problem parts */
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goto exit;
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pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
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/* Check for buggy part revisions */
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if (rev < 0x10 || rev > 0x12)
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goto exit;
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}
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/*
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* Ok we have the problem. Now set the PCI master grant to
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* occur every master grant. The apparent bug is that under high
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* PCI load (quite common in Linux of course) you can get data
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* loss when the CPU is held off the bus for 3 bus master requests
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* This happens to include the IDE controllers....
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*
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* VIA only apply this fix when an SB Live! is present but under
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* both Linux and Windows this isnt enough, and we have seen
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* corruption without SB Live! but with things like 3 UDMA IDE
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* controllers. So we ignore that bit of the VIA recommendation..
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*/
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pci_read_config_byte(dev, 0x76, &busarb);
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/* Set bit 4 and bi 5 of byte 76 to 0x01
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"Master priority rotation on every PCI master grant */
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busarb &= ~(1<<5);
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busarb |= (1<<4);
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pci_write_config_byte(dev, 0x76, busarb);
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printk(KERN_INFO "Applying VIA southbridge workaround.\n");
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exit:
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pci_dev_put(p);
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
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/*
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* VIA Apollo VP3 needs ETBF on BT848/878
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*/
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static void __devinit quirk_viaetbf(struct pci_dev *dev)
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{
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if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
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printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
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pci_pci_problems |= PCIPCI_VIAETBF;
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}
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
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static void __devinit quirk_vsfx(struct pci_dev *dev)
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{
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if ((pci_pci_problems&PCIPCI_VSFX)==0) {
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printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
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pci_pci_problems |= PCIPCI_VSFX;
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}
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
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/*
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* Ali Magik requires workarounds to be used by the drivers
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* that DMA to AGP space. Latency must be set to 0xA and triton
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* workaround applied too
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* [Info kindly provided by ALi]
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*/
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static void __init quirk_alimagik(struct pci_dev *dev)
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{
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if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
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printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
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pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
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}
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
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/*
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* Natoma has some interesting boundary conditions with Zoran stuff
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* at least
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*/
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static void __devinit quirk_natoma(struct pci_dev *dev)
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{
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if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
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printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
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pci_pci_problems |= PCIPCI_NATOMA;
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}
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
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/*
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* This chip can cause PCI parity errors if config register 0xA0 is read
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* while DMAs are occurring.
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*/
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static void __devinit quirk_citrine(struct pci_dev *dev)
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{
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dev->cfg_size = 0xA0;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
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/*
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* S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
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* If it's needed, re-allocate the region.
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*/
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static void __devinit quirk_s3_64M(struct pci_dev *dev)
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{
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struct resource *r = &dev->resource[0];
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if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
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r->start = 0;
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r->end = 0x3ffffff;
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
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static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr)
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{
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region &= ~(size-1);
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if (region) {
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struct resource *res = dev->resource + nr;
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res->name = pci_name(dev);
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res->start = region;
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res->end = region + size - 1;
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res->flags = IORESOURCE_IO;
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pci_claim_resource(dev, nr);
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}
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}
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/*
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* ATI Northbridge setups MCE the processor if you even
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* read somewhere between 0x3b0->0x3bb or read 0x3d3
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*/
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static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
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{
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printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
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/* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
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request_region(0x3b0, 0x0C, "RadeonIGP");
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request_region(0x3d3, 0x01, "RadeonIGP");
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
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/*
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* Let's make the southbridge information explicit instead
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* of having to worry about people probing the ACPI areas,
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* for example.. (Yes, it happens, and if you read the wrong
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* ACPI register it will put the machine to sleep with no
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* way of waking it up again. Bummer).
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*
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* ALI M7101: Two IO regions pointed to by words at
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* 0xE0 (64 bytes of ACPI registers)
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* 0xE2 (32 bytes of SMB registers)
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*/
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static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
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{
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u16 region;
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pci_read_config_word(dev, 0xE0, ®ion);
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quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
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pci_read_config_word(dev, 0xE2, ®ion);
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quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
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/*
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* PIIX4 ACPI: Two IO regions pointed to by longwords at
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* 0x40 (64 bytes of ACPI registers)
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* 0x90 (32 bytes of SMB registers)
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*/
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static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
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{
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u32 region;
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pci_read_config_dword(dev, 0x40, ®ion);
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quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
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pci_read_config_dword(dev, 0x90, ®ion);
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quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
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/*
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* ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
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* 0x40 (128 bytes of ACPI, GPIO & TCO registers)
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* 0x58 (64 bytes of GPIO I/O space)
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*/
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static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
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{
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u32 region;
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pci_read_config_dword(dev, 0x40, ®ion);
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quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES);
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pci_read_config_dword(dev, 0x58, ®ion);
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quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi );
|
|
|
|
/*
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* VIA ACPI: One IO region pointed to by longword at
|
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* 0x48 or 0x20 (256 bytes of ACPI registers)
|
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*/
|
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static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
|
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{
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u8 rev;
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u32 region;
|
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|
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pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
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if (rev & 0x10) {
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pci_read_config_dword(dev, 0x48, ®ion);
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region &= PCI_BASE_ADDRESS_IO_MASK;
|
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quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES);
|
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}
|
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}
|
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
|
|
|
|
/*
|
|
* VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
|
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* 0x48 (256 bytes of ACPI registers)
|
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* 0x70 (128 bytes of hardware monitoring register)
|
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* 0x90 (16 bytes of SMB registers)
|
|
*/
|
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static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
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{
|
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u16 hm;
|
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u32 smb;
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|
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quirk_vt82c586_acpi(dev);
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|
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pci_read_config_word(dev, 0x70, &hm);
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hm &= PCI_BASE_ADDRESS_IO_MASK;
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quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1);
|
|
|
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pci_read_config_dword(dev, 0x90, &smb);
|
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smb &= PCI_BASE_ADDRESS_IO_MASK;
|
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quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2);
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
|
|
|
|
|
|
#ifdef CONFIG_X86_IO_APIC
|
|
|
|
#include <asm/io_apic.h>
|
|
|
|
/*
|
|
* VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
|
|
* devices to the external APIC.
|
|
*
|
|
* TODO: When we have device-specific interrupt routers,
|
|
* this code will go away from quirks.
|
|
*/
|
|
static void __devinit quirk_via_ioapic(struct pci_dev *dev)
|
|
{
|
|
u8 tmp;
|
|
|
|
if (nr_ioapics < 1)
|
|
tmp = 0; /* nothing routed to external APIC */
|
|
else
|
|
tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
|
|
|
|
printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
|
|
tmp == 0 ? "Disa" : "Ena");
|
|
|
|
/* Offset 0x58: External APIC IRQ output control */
|
|
pci_write_config_byte (dev, 0x58, tmp);
|
|
}
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
|
|
|
|
/*
|
|
* The AMD io apic can hang the box when an apic irq is masked.
|
|
* We check all revs >= B0 (yet not in the pre production!) as the bug
|
|
* is currently marked NoFix
|
|
*
|
|
* We have multiple reports of hangs with this chipset that went away with
|
|
* noapic specified. For the moment we assume its the errata. We may be wrong
|
|
* of course. However the advice is demonstrably good even if so..
|
|
*/
|
|
static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
|
|
{
|
|
u8 rev;
|
|
|
|
pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
|
|
if (rev >= 0x02) {
|
|
printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
|
|
printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
|
|
}
|
|
}
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
|
|
|
|
static void __init quirk_ioapic_rmw(struct pci_dev *dev)
|
|
{
|
|
if (dev->devfn == 0 && dev->bus->number == 0)
|
|
sis_apic_bug = 1;
|
|
}
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
|
|
|
|
int pci_msi_quirk;
|
|
|
|
#define AMD8131_revA0 0x01
|
|
#define AMD8131_revB0 0x11
|
|
#define AMD8131_MISC 0x40
|
|
#define AMD8131_NIOAMODE_BIT 0
|
|
static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
|
|
{
|
|
unsigned char revid, tmp;
|
|
|
|
pci_msi_quirk = 1;
|
|
printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
|
|
|
|
if (nr_ioapics == 0)
|
|
return;
|
|
|
|
pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
|
|
if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
|
|
printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
|
|
pci_read_config_byte( dev, AMD8131_MISC, &tmp);
|
|
tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
|
|
pci_write_config_byte( dev, AMD8131_MISC, tmp);
|
|
}
|
|
}
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_APIC, quirk_amd_8131_ioapic );
|
|
|
|
static void __init quirk_svw_msi(struct pci_dev *dev)
|
|
{
|
|
pci_msi_quirk = 1;
|
|
printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
|
|
}
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi );
|
|
#endif /* CONFIG_X86_IO_APIC */
|
|
|
|
|
|
/*
|
|
* FIXME: it is questionable that quirk_via_acpi
|
|
* is needed. It shows up as an ISA bridge, and does not
|
|
* support the PCI_INTERRUPT_LINE register at all. Therefore
|
|
* it seems like setting the pci_dev's 'irq' to the
|
|
* value of the ACPI SCI interrupt is only done for convenience.
|
|
* -jgarzik
|
|
*/
|
|
static void __devinit quirk_via_acpi(struct pci_dev *d)
|
|
{
|
|
/*
|
|
* VIA ACPI device: SCI IRQ line in PCI config byte 0x42
|
|
*/
|
|
u8 irq;
|
|
pci_read_config_byte(d, 0x42, &irq);
|
|
irq &= 0xf;
|
|
if (irq && (irq != 2))
|
|
d->irq = irq;
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
|
|
|
|
/*
|
|
* Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
|
|
* devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
|
|
* when written, it makes an internal connection to the PIC.
|
|
* For these devices, this register is defined to be 4 bits wide.
|
|
* Normally this is fine. However for IO-APIC motherboards, or
|
|
* non-x86 architectures (yes Via exists on PPC among other places),
|
|
* we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
|
|
* interrupts delivered properly.
|
|
*/
|
|
static void quirk_via_irq(struct pci_dev *dev)
|
|
{
|
|
u8 irq, new_irq;
|
|
|
|
new_irq = dev->irq & 0xf;
|
|
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
|
|
if (new_irq != irq) {
|
|
printk(KERN_INFO "PCI: Via IRQ fixup for %s, from %d to %d\n",
|
|
pci_name(dev), irq, new_irq);
|
|
udelay(15); /* unknown if delay really needed */
|
|
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
|
|
}
|
|
}
|
|
DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_irq);
|
|
|
|
/*
|
|
* PIIX3 USB: We have to disable USB interrupts that are
|
|
* hardwired to PIRQD# and may be shared with an
|
|
* external device.
|
|
*
|
|
* Legacy Support Register (LEGSUP):
|
|
* bit13: USB PIRQ Enable (USBPIRQDEN),
|
|
* bit4: Trap/SMI On IRQ Enable (USBSMIEN).
|
|
*
|
|
* We mask out all r/wc bits, too.
|
|
*/
|
|
static void __devinit quirk_piix3_usb(struct pci_dev *dev)
|
|
{
|
|
u16 legsup;
|
|
|
|
pci_read_config_word(dev, 0xc0, &legsup);
|
|
legsup &= 0x50ef;
|
|
pci_write_config_word(dev, 0xc0, legsup);
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_2, quirk_piix3_usb );
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_2, quirk_piix3_usb );
|
|
|
|
/*
|
|
* VIA VT82C598 has its device ID settable and many BIOSes
|
|
* set it to the ID of VT82C597 for backward compatibility.
|
|
* We need to switch it off to be able to recognize the real
|
|
* type of the chip.
|
|
*/
|
|
static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
|
|
{
|
|
pci_write_config_byte(dev, 0xfc, 0);
|
|
pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
|
|
|
|
/*
|
|
* CardBus controllers have a legacy base address that enables them
|
|
* to respond as i82365 pcmcia controllers. We don't want them to
|
|
* do this even if the Linux CardBus driver is not loaded, because
|
|
* the Linux i82365 driver does not (and should not) handle CardBus.
|
|
*/
|
|
static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
|
|
{
|
|
if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
|
|
return;
|
|
pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
|
|
}
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
|
|
|
|
/*
|
|
* Following the PCI ordering rules is optional on the AMD762. I'm not
|
|
* sure what the designers were smoking but let's not inhale...
|
|
*
|
|
* To be fair to AMD, it follows the spec by default, its BIOS people
|
|
* who turn it off!
|
|
*/
|
|
static void __devinit quirk_amd_ordering(struct pci_dev *dev)
|
|
{
|
|
u32 pcic;
|
|
pci_read_config_dword(dev, 0x4C, &pcic);
|
|
if ((pcic&6)!=6) {
|
|
pcic |= 6;
|
|
printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
|
|
pci_write_config_dword(dev, 0x4C, pcic);
|
|
pci_read_config_dword(dev, 0x84, &pcic);
|
|
pcic |= (1<<23); /* Required in this mode */
|
|
pci_write_config_dword(dev, 0x84, pcic);
|
|
}
|
|
}
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
|
|
|
|
/*
|
|
* DreamWorks provided workaround for Dunord I-3000 problem
|
|
*
|
|
* This card decodes and responds to addresses not apparently
|
|
* assigned to it. We force a larger allocation to ensure that
|
|
* nothing gets put too close to it.
|
|
*/
|
|
static void __devinit quirk_dunord ( struct pci_dev * dev )
|
|
{
|
|
struct resource *r = &dev->resource [1];
|
|
r->start = 0;
|
|
r->end = 0xffffff;
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
|
|
|
|
/*
|
|
* i82380FB mobile docking controller: its PCI-to-PCI bridge
|
|
* is subtractive decoding (transparent), and does indicate this
|
|
* in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
|
|
* instead of 0x01.
|
|
*/
|
|
static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
|
|
{
|
|
dev->transparent = 1;
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
|
|
|
|
/*
|
|
* Common misconfiguration of the MediaGX/Geode PCI master that will
|
|
* reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
|
|
* datasheets found at http://www.national.com/ds/GX for info on what
|
|
* these bits do. <christer@weinigel.se>
|
|
*/
|
|
static void __init quirk_mediagx_master(struct pci_dev *dev)
|
|
{
|
|
u8 reg;
|
|
pci_read_config_byte(dev, 0x41, ®);
|
|
if (reg & 2) {
|
|
reg &= ~2;
|
|
printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
|
|
pci_write_config_byte(dev, 0x41, reg);
|
|
}
|
|
}
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
|
|
|
|
/*
|
|
* As per PCI spec, ignore base address registers 0-3 of the IDE controllers
|
|
* running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
|
|
* secondary channels respectively). If the device reports Compatible mode
|
|
* but does use BAR0-3 for address decoding, we assume that firmware has
|
|
* programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
|
|
* Exceptions (if they exist) must be handled in chip/architecture specific
|
|
* fixups.
|
|
*
|
|
* Note: for non x86 people. You may need an arch specific quirk to handle
|
|
* moving IDE devices to native mode as well. Some plug in card devices power
|
|
* up in compatible mode and assume the BIOS will adjust them.
|
|
*
|
|
* Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
|
|
* we do now ? We don't want is pci_enable_device to come along
|
|
* and assign new resources. Both approaches work for that.
|
|
*/
|
|
static void __devinit quirk_ide_bases(struct pci_dev *dev)
|
|
{
|
|
struct resource *res;
|
|
int first_bar = 2, last_bar = 0;
|
|
|
|
if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
|
|
return;
|
|
|
|
res = &dev->resource[0];
|
|
|
|
/* primary channel: ProgIf bit 0, BAR0, BAR1 */
|
|
if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
|
|
res[0].start = res[0].end = res[0].flags = 0;
|
|
res[1].start = res[1].end = res[1].flags = 0;
|
|
first_bar = 0;
|
|
last_bar = 1;
|
|
}
|
|
|
|
/* secondary channel: ProgIf bit 2, BAR2, BAR3 */
|
|
if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
|
|
res[2].start = res[2].end = res[2].flags = 0;
|
|
res[3].start = res[3].end = res[3].flags = 0;
|
|
last_bar = 3;
|
|
}
|
|
|
|
if (!last_bar)
|
|
return;
|
|
|
|
printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
|
|
first_bar, last_bar, pci_name(dev));
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases);
|
|
|
|
/*
|
|
* Ensure C0 rev restreaming is off. This is normally done by
|
|
* the BIOS but in the odd case it is not the results are corruption
|
|
* hence the presence of a Linux check
|
|
*/
|
|
static void __init quirk_disable_pxb(struct pci_dev *pdev)
|
|
{
|
|
u16 config;
|
|
u8 rev;
|
|
|
|
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
|
|
if (rev != 0x04) /* Only C0 requires this */
|
|
return;
|
|
pci_read_config_word(pdev, 0x40, &config);
|
|
if (config & (1<<6)) {
|
|
config &= ~(1<<6);
|
|
pci_write_config_word(pdev, 0x40, config);
|
|
printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
|
|
}
|
|
}
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
|
|
|
|
|
|
/*
|
|
* Serverworks CSB5 IDE does not fully support native mode
|
|
*/
|
|
static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
|
|
{
|
|
u8 prog;
|
|
pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
|
|
if (prog & 5) {
|
|
prog &= ~5;
|
|
pdev->class &= ~5;
|
|
pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
|
|
/* need to re-assign BARs for compat mode */
|
|
quirk_ide_bases(pdev);
|
|
}
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
|
|
|
|
/*
|
|
* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
|
|
*/
|
|
static void __init quirk_ide_samemode(struct pci_dev *pdev)
|
|
{
|
|
u8 prog;
|
|
|
|
pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
|
|
|
|
if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
|
|
printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
|
|
prog &= ~5;
|
|
pdev->class &= ~5;
|
|
pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
|
|
/* need to re-assign BARs for compat mode */
|
|
quirk_ide_bases(pdev);
|
|
}
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
|
|
|
|
/* This was originally an Alpha specific thing, but it really fits here.
|
|
* The i82375 PCI/EISA bridge appears as non-classified. Fix that.
|
|
*/
|
|
static void __init quirk_eisa_bridge(struct pci_dev *dev)
|
|
{
|
|
dev->class = PCI_CLASS_BRIDGE_EISA << 8;
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
|
|
|
|
/*
|
|
* On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
|
|
* is not activated. The myth is that Asus said that they do not want the
|
|
* users to be irritated by just another PCI Device in the Win98 device
|
|
* manager. (see the file prog/hotplug/README.p4b in the lm_sensors
|
|
* package 2.7.0 for details)
|
|
*
|
|
* The SMBus PCI Device can be activated by setting a bit in the ICH LPC
|
|
* bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
|
|
* becomes necessary to do this tweak in two steps -- I've chosen the Host
|
|
* bridge as trigger.
|
|
*/
|
|
static int __initdata asus_hides_smbus = 0;
|
|
|
|
static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
|
|
{
|
|
if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
|
|
if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
|
|
switch(dev->subsystem_device) {
|
|
case 0x8025: /* P4B-LX */
|
|
case 0x8070: /* P4B */
|
|
case 0x8088: /* P4B533 */
|
|
case 0x1626: /* L3C notebook */
|
|
asus_hides_smbus = 1;
|
|
}
|
|
if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
|
|
switch(dev->subsystem_device) {
|
|
case 0x80b1: /* P4GE-V */
|
|
case 0x80b2: /* P4PE */
|
|
case 0x8093: /* P4B533-V */
|
|
asus_hides_smbus = 1;
|
|
}
|
|
if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
|
|
switch(dev->subsystem_device) {
|
|
case 0x8030: /* P4T533 */
|
|
asus_hides_smbus = 1;
|
|
}
|
|
if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
|
|
switch (dev->subsystem_device) {
|
|
case 0x8070: /* P4G8X Deluxe */
|
|
asus_hides_smbus = 1;
|
|
}
|
|
if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
|
|
switch (dev->subsystem_device) {
|
|
case 0x1751: /* M2N notebook */
|
|
case 0x1821: /* M5N notebook */
|
|
asus_hides_smbus = 1;
|
|
}
|
|
if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
|
|
switch (dev->subsystem_device) {
|
|
case 0x184b: /* W1N notebook */
|
|
case 0x186a: /* M6Ne notebook */
|
|
asus_hides_smbus = 1;
|
|
}
|
|
} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
|
|
if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
|
|
switch(dev->subsystem_device) {
|
|
case 0x088C: /* HP Compaq nc8000 */
|
|
case 0x0890: /* HP Compaq nc6000 */
|
|
asus_hides_smbus = 1;
|
|
}
|
|
if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
|
|
switch (dev->subsystem_device) {
|
|
case 0x12bc: /* HP D330L */
|
|
asus_hides_smbus = 1;
|
|
}
|
|
} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) {
|
|
if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
|
|
switch(dev->subsystem_device) {
|
|
case 0x0001: /* Toshiba Satellite A40 */
|
|
asus_hides_smbus = 1;
|
|
}
|
|
if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
|
|
switch(dev->subsystem_device) {
|
|
case 0x0001: /* Toshiba Tecra M2 */
|
|
asus_hides_smbus = 1;
|
|
}
|
|
} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
|
|
if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
|
|
switch(dev->subsystem_device) {
|
|
case 0xC00C: /* Samsung P35 notebook */
|
|
asus_hides_smbus = 1;
|
|
}
|
|
}
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
|
|
|
|
static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
|
|
{
|
|
u16 val;
|
|
|
|
if (likely(!asus_hides_smbus))
|
|
return;
|
|
|
|
pci_read_config_word(dev, 0xF2, &val);
|
|
if (val & 0x8) {
|
|
pci_write_config_word(dev, 0xF2, val & (~0x8));
|
|
pci_read_config_word(dev, 0xF2, &val);
|
|
if (val & 0x8)
|
|
printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
|
|
else
|
|
printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
|
|
}
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
|
|
|
|
/*
|
|
* SiS 96x south bridge: BIOS typically hides SMBus device...
|
|
*/
|
|
static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
|
|
{
|
|
u8 val = 0;
|
|
printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
|
|
pci_read_config_byte(dev, 0x77, &val);
|
|
pci_write_config_byte(dev, 0x77, val & ~0x10);
|
|
pci_read_config_byte(dev, 0x77, &val);
|
|
}
|
|
|
|
|
|
#define UHCI_USBLEGSUP 0xc0 /* legacy support */
|
|
#define UHCI_USBCMD 0 /* command register */
|
|
#define UHCI_USBSTS 2 /* status register */
|
|
#define UHCI_USBINTR 4 /* interrupt register */
|
|
#define UHCI_USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
|
|
#define UHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
|
|
#define UHCI_USBCMD_GRESET (1 << 2) /* Global reset */
|
|
#define UHCI_USBCMD_CONFIGURE (1 << 6) /* config semaphore */
|
|
#define UHCI_USBSTS_HALTED (1 << 5) /* HCHalted bit */
|
|
|
|
#define OHCI_CONTROL 0x04
|
|
#define OHCI_CMDSTATUS 0x08
|
|
#define OHCI_INTRSTATUS 0x0c
|
|
#define OHCI_INTRENABLE 0x10
|
|
#define OHCI_INTRDISABLE 0x14
|
|
#define OHCI_OCR (1 << 3) /* ownership change request */
|
|
#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
|
|
#define OHCI_INTR_OC (1 << 30) /* ownership change */
|
|
|
|
#define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
|
|
#define EHCI_USBCMD 0 /* command register */
|
|
#define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
|
|
#define EHCI_USBSTS 4 /* status register */
|
|
#define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
|
|
#define EHCI_USBINTR 8 /* interrupt register */
|
|
#define EHCI_USBLEGSUP 0 /* legacy support register */
|
|
#define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
|
|
#define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
|
|
#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
|
|
#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
|
|
|
|
int usb_early_handoff __devinitdata = 0;
|
|
static int __init usb_handoff_early(char *str)
|
|
{
|
|
usb_early_handoff = 1;
|
|
return 0;
|
|
}
|
|
__setup("usb-handoff", usb_handoff_early);
|
|
|
|
static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
|
|
{
|
|
unsigned long base = 0;
|
|
int wait_time, delta;
|
|
u16 val, sts;
|
|
int i;
|
|
|
|
for (i = 0; i < PCI_ROM_RESOURCE; i++)
|
|
if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
|
|
base = pci_resource_start(pdev, i);
|
|
break;
|
|
}
|
|
|
|
if (!base)
|
|
return;
|
|
|
|
/*
|
|
* stop controller
|
|
*/
|
|
sts = inw(base + UHCI_USBSTS);
|
|
val = inw(base + UHCI_USBCMD);
|
|
val &= ~(u16)(UHCI_USBCMD_RUN | UHCI_USBCMD_CONFIGURE);
|
|
outw(val, base + UHCI_USBCMD);
|
|
|
|
/*
|
|
* wait while it stops if it was running
|
|
*/
|
|
if ((sts & UHCI_USBSTS_HALTED) == 0)
|
|
{
|
|
wait_time = 1000;
|
|
delta = 100;
|
|
|
|
do {
|
|
outw(0x1f, base + UHCI_USBSTS);
|
|
udelay(delta);
|
|
wait_time -= delta;
|
|
val = inw(base + UHCI_USBSTS);
|
|
if (val & UHCI_USBSTS_HALTED)
|
|
break;
|
|
} while (wait_time > 0);
|
|
}
|
|
|
|
/*
|
|
* disable interrupts & legacy support
|
|
*/
|
|
outw(0, base + UHCI_USBINTR);
|
|
outw(0x1f, base + UHCI_USBSTS);
|
|
pci_read_config_word(pdev, UHCI_USBLEGSUP, &val);
|
|
if (val & 0xbf)
|
|
pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_DEFAULT);
|
|
|
|
}
|
|
|
|
static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
|
|
{
|
|
void __iomem *base;
|
|
int wait_time;
|
|
|
|
base = ioremap_nocache(pci_resource_start(pdev, 0),
|
|
pci_resource_len(pdev, 0));
|
|
if (base == NULL) return;
|
|
|
|
if (readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
|
|
wait_time = 500; /* 0.5 seconds */
|
|
writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
|
|
writel(OHCI_OCR, base + OHCI_CMDSTATUS);
|
|
while (wait_time > 0 &&
|
|
readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
|
|
wait_time -= 10;
|
|
msleep(10);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* disable interrupts
|
|
*/
|
|
writel(~(u32)0, base + OHCI_INTRDISABLE);
|
|
writel(~(u32)0, base + OHCI_INTRSTATUS);
|
|
|
|
iounmap(base);
|
|
}
|
|
|
|
static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
|
|
{
|
|
int wait_time, delta;
|
|
void __iomem *base, *op_reg_base;
|
|
u32 hcc_params, val, temp;
|
|
u8 cap_length;
|
|
|
|
base = ioremap_nocache(pci_resource_start(pdev, 0),
|
|
pci_resource_len(pdev, 0));
|
|
if (base == NULL) return;
|
|
|
|
cap_length = readb(base);
|
|
op_reg_base = base + cap_length;
|
|
hcc_params = readl(base + EHCI_HCC_PARAMS);
|
|
hcc_params = (hcc_params >> 8) & 0xff;
|
|
if (hcc_params) {
|
|
pci_read_config_dword(pdev,
|
|
hcc_params + EHCI_USBLEGSUP,
|
|
&val);
|
|
if (((val & 0xff) == 1) && (val & EHCI_USBLEGSUP_BIOS)) {
|
|
/*
|
|
* Ok, BIOS is in smm mode, try to hand off...
|
|
*/
|
|
pci_read_config_dword(pdev,
|
|
hcc_params + EHCI_USBLEGCTLSTS,
|
|
&temp);
|
|
pci_write_config_dword(pdev,
|
|
hcc_params + EHCI_USBLEGCTLSTS,
|
|
temp | EHCI_USBLEGCTLSTS_SOOE);
|
|
val |= EHCI_USBLEGSUP_OS;
|
|
pci_write_config_dword(pdev,
|
|
hcc_params + EHCI_USBLEGSUP,
|
|
val);
|
|
|
|
wait_time = 500;
|
|
do {
|
|
msleep(10);
|
|
wait_time -= 10;
|
|
pci_read_config_dword(pdev,
|
|
hcc_params + EHCI_USBLEGSUP,
|
|
&val);
|
|
} while (wait_time && (val & EHCI_USBLEGSUP_BIOS));
|
|
if (!wait_time) {
|
|
/*
|
|
* well, possibly buggy BIOS...
|
|
*/
|
|
printk(KERN_WARNING "EHCI early BIOS handoff "
|
|
"failed (BIOS bug ?)\n");
|
|
pci_write_config_dword(pdev,
|
|
hcc_params + EHCI_USBLEGSUP,
|
|
EHCI_USBLEGSUP_OS);
|
|
pci_write_config_dword(pdev,
|
|
hcc_params + EHCI_USBLEGCTLSTS,
|
|
0);
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* halt EHCI & disable its interrupts in any case
|
|
*/
|
|
val = readl(op_reg_base + EHCI_USBSTS);
|
|
if ((val & EHCI_USBSTS_HALTED) == 0) {
|
|
val = readl(op_reg_base + EHCI_USBCMD);
|
|
val &= ~EHCI_USBCMD_RUN;
|
|
writel(val, op_reg_base + EHCI_USBCMD);
|
|
|
|
wait_time = 2000;
|
|
delta = 100;
|
|
do {
|
|
writel(0x3f, op_reg_base + EHCI_USBSTS);
|
|
udelay(delta);
|
|
wait_time -= delta;
|
|
val = readl(op_reg_base + EHCI_USBSTS);
|
|
if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
|
|
break;
|
|
}
|
|
} while (wait_time > 0);
|
|
}
|
|
writel(0, op_reg_base + EHCI_USBINTR);
|
|
writel(0x3f, op_reg_base + EHCI_USBSTS);
|
|
|
|
iounmap(base);
|
|
|
|
return;
|
|
}
|
|
|
|
|
|
|
|
static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
|
|
{
|
|
if (!usb_early_handoff)
|
|
return;
|
|
|
|
if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x00)) { /* UHCI */
|
|
quirk_usb_handoff_uhci(pdev);
|
|
} else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10)) { /* OHCI */
|
|
quirk_usb_handoff_ohci(pdev);
|
|
} else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x20)) { /* EHCI */
|
|
quirk_usb_disable_ehci(pdev);
|
|
}
|
|
|
|
return;
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);
|
|
|
|
/*
|
|
* ... This is further complicated by the fact that some SiS96x south
|
|
* bridges pretend to be 85C503/5513 instead. In that case see if we
|
|
* spotted a compatible north bridge to make sure.
|
|
* (pci_find_device doesn't work yet)
|
|
*
|
|
* We can also enable the sis96x bit in the discovery register..
|
|
*/
|
|
static int __devinitdata sis_96x_compatible = 0;
|
|
|
|
#define SIS_DETECT_REGISTER 0x40
|
|
|
|
static void __init quirk_sis_503(struct pci_dev *dev)
|
|
{
|
|
u8 reg;
|
|
u16 devid;
|
|
|
|
pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
|
|
pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
|
|
pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
|
|
if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
|
|
pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
|
|
return;
|
|
}
|
|
|
|
/* Make people aware that we changed the config.. */
|
|
printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
|
|
|
|
/*
|
|
* Ok, it now shows up as a 96x.. The 96x quirks are after
|
|
* the 503 quirk in the quirk table, so they'll automatically
|
|
* run and enable things like the SMBus device
|
|
*/
|
|
dev->device = devid;
|
|
}
|
|
|
|
static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
|
|
{
|
|
sis_96x_compatible = 1;
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible );
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible );
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible );
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible );
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible );
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible );
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
|
|
|
|
#ifdef CONFIG_X86_IO_APIC
|
|
static void __init quirk_alder_ioapic(struct pci_dev *pdev)
|
|
{
|
|
int i;
|
|
|
|
if ((pdev->class >> 8) != 0xff00)
|
|
return;
|
|
|
|
/* the first BAR is the location of the IO APIC...we must
|
|
* not touch this (and it's already covered by the fixmap), so
|
|
* forcibly insert it into the resource tree */
|
|
if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
|
|
insert_resource(&iomem_resource, &pdev->resource[0]);
|
|
|
|
/* The next five BARs all seem to be rubbish, so just clean
|
|
* them out */
|
|
for (i=1; i < 6; i++) {
|
|
memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
|
|
}
|
|
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
|
|
#endif
|
|
|
|
#ifdef CONFIG_SCSI_SATA
|
|
static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev)
|
|
{
|
|
u8 prog, comb, tmp;
|
|
int ich = 0;
|
|
|
|
/*
|
|
* Narrow down to Intel SATA PCI devices.
|
|
*/
|
|
switch (pdev->device) {
|
|
/* PCI ids taken from drivers/scsi/ata_piix.c */
|
|
case 0x24d1:
|
|
case 0x24df:
|
|
case 0x25a3:
|
|
case 0x25b0:
|
|
ich = 5;
|
|
break;
|
|
case 0x2651:
|
|
case 0x2652:
|
|
case 0x2653:
|
|
case 0x2680: /* ESB2 */
|
|
ich = 6;
|
|
break;
|
|
case 0x27c0:
|
|
case 0x27c4:
|
|
ich = 7;
|
|
break;
|
|
default:
|
|
/* we do not handle this PCI device */
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Read combined mode register.
|
|
*/
|
|
pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
|
|
|
|
if (ich == 5) {
|
|
tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
|
|
if (tmp == 0x4) /* bits 10x */
|
|
comb = (1 << 0); /* SATA port 0, PATA port 1 */
|
|
else if (tmp == 0x6) /* bits 11x */
|
|
comb = (1 << 2); /* PATA port 0, SATA port 1 */
|
|
else
|
|
return; /* not in combined mode */
|
|
} else {
|
|
WARN_ON((ich != 6) && (ich != 7));
|
|
tmp &= 0x3; /* interesting bits 1:0 */
|
|
if (tmp & (1 << 0))
|
|
comb = (1 << 2); /* PATA port 0, SATA port 1 */
|
|
else if (tmp & (1 << 1))
|
|
comb = (1 << 0); /* SATA port 0, PATA port 1 */
|
|
else
|
|
return; /* not in combined mode */
|
|
}
|
|
|
|
/*
|
|
* Read programming interface register.
|
|
* (Tells us if it's legacy or native mode)
|
|
*/
|
|
pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
|
|
|
|
/* if SATA port is in native mode, we're ok. */
|
|
if (prog & comb)
|
|
return;
|
|
|
|
/* SATA port is in legacy mode. Reserve port so that
|
|
* IDE driver does not attempt to use it. If request_region
|
|
* fails, it will be obvious at boot time, so we don't bother
|
|
* checking return values.
|
|
*/
|
|
if (comb == (1 << 0))
|
|
request_region(0x1f0, 8, "libata"); /* port 0 */
|
|
else
|
|
request_region(0x170, 8, "libata"); /* port 1 */
|
|
}
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined );
|
|
#endif /* CONFIG_SCSI_SATA */
|
|
|
|
|
|
int pcie_mch_quirk;
|
|
|
|
static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
|
|
{
|
|
pcie_mch_quirk = 1;
|
|
}
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
|
|
|
|
static void __devinit quirk_netmos(struct pci_dev *dev)
|
|
{
|
|
unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
|
|
unsigned int num_serial = dev->subsystem_device & 0xf;
|
|
|
|
/*
|
|
* These Netmos parts are multiport serial devices with optional
|
|
* parallel ports. Even when parallel ports are present, they
|
|
* are identified as class SERIAL, which means the serial driver
|
|
* will claim them. To prevent this, mark them as class OTHER.
|
|
* These combo devices should be claimed by parport_serial.
|
|
*
|
|
* The subdevice ID is of the form 0x00PS, where <P> is the number
|
|
* of parallel ports and <S> is the number of serial ports.
|
|
*/
|
|
switch (dev->device) {
|
|
case PCI_DEVICE_ID_NETMOS_9735:
|
|
case PCI_DEVICE_ID_NETMOS_9745:
|
|
case PCI_DEVICE_ID_NETMOS_9835:
|
|
case PCI_DEVICE_ID_NETMOS_9845:
|
|
case PCI_DEVICE_ID_NETMOS_9855:
|
|
if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
|
|
num_parallel) {
|
|
printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
|
|
"%u serial); changing class SERIAL to OTHER "
|
|
"(use parport_serial)\n",
|
|
dev->device, num_parallel, num_serial);
|
|
dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
|
|
(dev->class & 0xff);
|
|
}
|
|
}
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
|
|
|
|
static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
|
|
{
|
|
while (f < end) {
|
|
if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
|
|
(f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
|
|
pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
|
|
f->hook(dev);
|
|
}
|
|
f++;
|
|
}
|
|
}
|
|
|
|
extern struct pci_fixup __start_pci_fixups_early[];
|
|
extern struct pci_fixup __end_pci_fixups_early[];
|
|
extern struct pci_fixup __start_pci_fixups_header[];
|
|
extern struct pci_fixup __end_pci_fixups_header[];
|
|
extern struct pci_fixup __start_pci_fixups_final[];
|
|
extern struct pci_fixup __end_pci_fixups_final[];
|
|
extern struct pci_fixup __start_pci_fixups_enable[];
|
|
extern struct pci_fixup __end_pci_fixups_enable[];
|
|
|
|
|
|
void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
|
|
{
|
|
struct pci_fixup *start, *end;
|
|
|
|
switch(pass) {
|
|
case pci_fixup_early:
|
|
start = __start_pci_fixups_early;
|
|
end = __end_pci_fixups_early;
|
|
break;
|
|
|
|
case pci_fixup_header:
|
|
start = __start_pci_fixups_header;
|
|
end = __end_pci_fixups_header;
|
|
break;
|
|
|
|
case pci_fixup_final:
|
|
start = __start_pci_fixups_final;
|
|
end = __end_pci_fixups_final;
|
|
break;
|
|
|
|
case pci_fixup_enable:
|
|
start = __start_pci_fixups_enable;
|
|
end = __end_pci_fixups_enable;
|
|
break;
|
|
|
|
default:
|
|
/* stupid compiler warning, you would think with an enum... */
|
|
return;
|
|
}
|
|
pci_do_fixups(dev, start, end);
|
|
}
|
|
|
|
EXPORT_SYMBOL(pcie_mch_quirk);
|
|
#ifdef CONFIG_HOTPLUG
|
|
EXPORT_SYMBOL(pci_fixup_device);
|
|
#endif
|