forked from Minki/linux
ca3e35c7a3
The SAI mainly has the following clocks:
bus clock
control and configure registers and to generate synchronous
interrupts and DMA requests.
mclk1, mclk2, mclk3
to generate the bit clock when the receiver or transmitter is
configured for an internally generated bit clock.
So this patch adds these clocks and their clock controls to the driver.
[ To concern the old DTB cases, I've added a bit of extra code to make
the driver compatible with them. And by marking clock NULL if failed
to get, the clk_prepare() or clk_get_rate() would easily return 0
so no further path should be broken. -- by Nicolin ]
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Acked-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
44 lines
1.8 KiB
Plaintext
44 lines
1.8 KiB
Plaintext
Freescale Synchronous Audio Interface (SAI).
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The SAI is based on I2S module that used communicating with audio codecs,
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which provides a synchronous audio interface that supports fullduplex
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serial interfaces with frame synchronization such as I2S, AC97, TDM, and
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codec/DSP interfaces.
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Required properties:
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- compatible: Compatible list, contains "fsl,vf610-sai" or "fsl,imx6sx-sai".
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- reg: Offset and length of the register set for the device.
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- clocks: Must contain an entry for each entry in clock-names.
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- clock-names : Must include the "bus" for register access and "mclk1" "mclk2"
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"mclk3" for bit clock and frame clock providing.
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- dmas : Generic dma devicetree binding as described in
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Documentation/devicetree/bindings/dma/dma.txt.
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- dma-names : Two dmas have to be defined, "tx" and "rx".
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- pinctrl-names: Must contain a "default" entry.
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- pinctrl-NNN: One property must exist for each entry in pinctrl-names.
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See ../pinctrl/pinctrl-bindings.txt for details of the property values.
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- big-endian-regs: If this property is absent, the little endian mode will
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be in use as default, or the big endian mode will be in use for all the
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device registers.
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- big-endian-data: If this property is absent, the little endian mode will
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be in use as default, or the big endian mode will be in use for all the
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fifo data.
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Example:
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sai2: sai@40031000 {
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compatible = "fsl,vf610-sai";
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reg = <0x40031000 0x1000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai2_1>;
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clocks = <&clks VF610_CLK_PLATFORM_BUS>,
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<&clks VF610_CLK_SAI2>,
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<&clks 0>, <&clks 0>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dma-names = "tx", "rx";
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dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
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<&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
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big-endian-regs;
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big-endian-data;
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};
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