forked from Minki/linux
fc1acf317b
Add support for the Image Processing Unit (IPU) found in all Ingenic
SoCs.
The IPU can upscale and downscale a source frame of arbitrary size
ranging from 4x4 to 4096x4096 on newer SoCs, with bicubic filtering
on newer SoCs, bilinear filtering on older SoCs. Nearest-neighbour can
also be obtained with proper coefficients.
Starting from the JZ4725B, the IPU supports a mode where its output is
sent directly to the LCDC, without having to be written to RAM first.
This makes it possible to use the IPU as a DRM plane on the compatible
SoCs, and have it convert and scale anything the userspace asks for to
what's available for the display.
Regarding pixel formats, older SoCs support packed YUV 4:2:2 and various
planar YUV formats. Newer SoCs introduced support for RGB.
Since the IPU is a separate hardware block, to make it work properly the
Ingenic DRM driver will now register itself as a component master in
case the IPU driver has been enabled in the config.
When enabled in the config, the CRTC will see the IPU as a second primary
plane. It cannot be enabled at the same time as the regular primary
plane. It has the same priority, which means that it will also display
below the overlay plane.
v2: - ingenic-ipu is no longer its own module. It will be built
into the ingenic-drm module.
- If enabled in the config, both the core driver and the IPU
driver will register as components; otherwise the core
driver will bypass that and call the ingenic_drm_bind()
function directly.
- Since both files now build into the same module, the
symbols previously exported as GPL are not exported anymore,
since they are only used internally.
- Fix SPDX license header in ingenic-ipu.h
- Avoid using 'for(;;);' loops without trailing statement(s)
v3: - Pass priv structure to IRQ handler; that way we don't hardcode
the expectation that the IPU plane is at index #0.
- Rework osd_changed() to account for src_* changes
- Add multiplanar YUV 4:4:4 support
- Commit fb addresses to HW at vblank, since addr registers are
not shadow registers
- Probe IPU component later so that IPU plane is last
- Fix driver not working on IPU-less hardware
- Use IPU driver's name as the IRQ name to avoid having two
'ingenic-drm' in /proc/interrupts
- Fix IPU only working for still images on JZ4725B
- Add a bit more code comments
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20200716163846.174790-10-paul@crapouillou.net
110 lines
4.1 KiB
C
110 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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//
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// Ingenic JZ47xx IPU - Register definitions and private API
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//
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// Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net>
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#ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_IPU_H
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#define DRIVERS_GPU_DRM_INGENIC_INGENIC_IPU_H
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#include <linux/bitops.h>
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#define JZ_REG_IPU_CTRL 0x00
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#define JZ_REG_IPU_STATUS 0x04
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#define JZ_REG_IPU_D_FMT 0x08
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#define JZ_REG_IPU_Y_ADDR 0x0c
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#define JZ_REG_IPU_U_ADDR 0x10
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#define JZ_REG_IPU_V_ADDR 0x14
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#define JZ_REG_IPU_IN_GS 0x18
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#define JZ_REG_IPU_Y_STRIDE 0x1c
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#define JZ_REG_IPU_UV_STRIDE 0x20
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#define JZ_REG_IPU_OUT_ADDR 0x24
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#define JZ_REG_IPU_OUT_GS 0x28
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#define JZ_REG_IPU_OUT_STRIDE 0x2c
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#define JZ_REG_IPU_RSZ_COEF_INDEX 0x30
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#define JZ_REG_IPU_CSC_C0_COEF 0x34
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#define JZ_REG_IPU_CSC_C1_COEF 0x38
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#define JZ_REG_IPU_CSC_C2_COEF 0x3c
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#define JZ_REG_IPU_CSC_C3_COEF 0x40
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#define JZ_REG_IPU_CSC_C4_COEF 0x44
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#define JZ_REG_IPU_HRSZ_COEF_LUT 0x48
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#define JZ_REG_IPU_VRSZ_COEF_LUT 0x4c
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#define JZ_REG_IPU_CSC_OFFSET 0x50
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#define JZ_REG_IPU_Y_PHY_T_ADDR 0x54
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#define JZ_REG_IPU_U_PHY_T_ADDR 0x58
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#define JZ_REG_IPU_V_PHY_T_ADDR 0x5c
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#define JZ_REG_IPU_OUT_PHY_T_ADDR 0x60
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#define JZ_IPU_CTRL_ADDR_SEL BIT(20)
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#define JZ_IPU_CTRL_ZOOM_SEL BIT(18)
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#define JZ_IPU_CTRL_DFIX_SEL BIT(17)
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#define JZ_IPU_CTRL_LCDC_SEL BIT(11)
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#define JZ_IPU_CTRL_SPKG_SEL BIT(10)
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#define JZ_IPU_CTRL_VSCALE BIT(9)
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#define JZ_IPU_CTRL_HSCALE BIT(8)
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#define JZ_IPU_CTRL_STOP BIT(7)
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#define JZ_IPU_CTRL_RST BIT(6)
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#define JZ_IPU_CTRL_FM_IRQ_EN BIT(5)
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#define JZ_IPU_CTRL_CSC_EN BIT(4)
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#define JZ_IPU_CTRL_VRSZ_EN BIT(3)
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#define JZ_IPU_CTRL_HRSZ_EN BIT(2)
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#define JZ_IPU_CTRL_RUN BIT(1)
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#define JZ_IPU_CTRL_CHIP_EN BIT(0)
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#define JZ_IPU_STATUS_OUT_END BIT(0)
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#define JZ_IPU_IN_GS_H_LSB 0x0
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#define JZ_IPU_IN_GS_W_LSB 0x10
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#define JZ_IPU_OUT_GS_H_LSB 0x0
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#define JZ_IPU_OUT_GS_W_LSB 0x10
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#define JZ_IPU_Y_STRIDE_Y_LSB 0
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#define JZ_IPU_UV_STRIDE_U_LSB 16
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#define JZ_IPU_UV_STRIDE_V_LSB 0
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#define JZ_IPU_D_FMT_IN_FMT_LSB 0
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#define JZ_IPU_D_FMT_IN_FMT_RGB555 (0x0 << JZ_IPU_D_FMT_IN_FMT_LSB)
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#define JZ_IPU_D_FMT_IN_FMT_YUV420 (0x0 << JZ_IPU_D_FMT_IN_FMT_LSB)
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#define JZ_IPU_D_FMT_IN_FMT_YUV422 (0x1 << JZ_IPU_D_FMT_IN_FMT_LSB)
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#define JZ_IPU_D_FMT_IN_FMT_RGB888 (0x2 << JZ_IPU_D_FMT_IN_FMT_LSB)
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#define JZ_IPU_D_FMT_IN_FMT_YUV444 (0x2 << JZ_IPU_D_FMT_IN_FMT_LSB)
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#define JZ_IPU_D_FMT_IN_FMT_RGB565 (0x3 << JZ_IPU_D_FMT_IN_FMT_LSB)
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#define JZ_IPU_D_FMT_YUV_FMT_LSB 2
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#define JZ_IPU_D_FMT_YUV_Y1UY0V (0x0 << JZ_IPU_D_FMT_YUV_FMT_LSB)
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#define JZ_IPU_D_FMT_YUV_Y1VY0U (0x1 << JZ_IPU_D_FMT_YUV_FMT_LSB)
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#define JZ_IPU_D_FMT_YUV_UY1VY0 (0x2 << JZ_IPU_D_FMT_YUV_FMT_LSB)
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#define JZ_IPU_D_FMT_YUV_VY1UY0 (0x3 << JZ_IPU_D_FMT_YUV_FMT_LSB)
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#define JZ_IPU_D_FMT_IN_FMT_YUV411 (0x3 << JZ_IPU_D_FMT_IN_FMT_LSB)
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#define JZ_IPU_D_FMT_OUT_FMT_LSB 19
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#define JZ_IPU_D_FMT_OUT_FMT_RGB555 (0x0 << JZ_IPU_D_FMT_OUT_FMT_LSB)
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#define JZ_IPU_D_FMT_OUT_FMT_RGB565 (0x1 << JZ_IPU_D_FMT_OUT_FMT_LSB)
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#define JZ_IPU_D_FMT_OUT_FMT_RGB888 (0x2 << JZ_IPU_D_FMT_OUT_FMT_LSB)
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#define JZ_IPU_D_FMT_OUT_FMT_YUV422 (0x3 << JZ_IPU_D_FMT_OUT_FMT_LSB)
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#define JZ_IPU_D_FMT_OUT_FMT_RGBAAA (0x4 << JZ_IPU_D_FMT_OUT_FMT_LSB)
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#define JZ_IPU_D_FMT_RGB_OUT_OFT_LSB 22
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#define JZ_IPU_D_FMT_RGB_OUT_OFT_RGB (0x0 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
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#define JZ_IPU_D_FMT_RGB_OUT_OFT_RBG (0x1 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
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#define JZ_IPU_D_FMT_RGB_OUT_OFT_GBR (0x2 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
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#define JZ_IPU_D_FMT_RGB_OUT_OFT_GRB (0x3 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
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#define JZ_IPU_D_FMT_RGB_OUT_OFT_BRG (0x4 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
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#define JZ_IPU_D_FMT_RGB_OUT_OFT_BGR (0x5 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
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#define JZ4725B_IPU_RSZ_LUT_COEF_LSB 2
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#define JZ4725B_IPU_RSZ_LUT_COEF_MASK 0x7ff
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#define JZ4725B_IPU_RSZ_LUT_IN_EN BIT(1)
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#define JZ4725B_IPU_RSZ_LUT_OUT_EN BIT(0)
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#define JZ4760_IPU_RSZ_COEF20_LSB 6
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#define JZ4760_IPU_RSZ_COEF31_LSB 17
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#define JZ4760_IPU_RSZ_COEF_MASK 0x7ff
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#define JZ4760_IPU_RSZ_OFFSET_LSB 1
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#define JZ4760_IPU_RSZ_OFFSET_MASK 0x1f
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#define JZ_IPU_CSC_OFFSET_CHROMA_LSB 16
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#define JZ_IPU_CSC_OFFSET_LUMA_LSB 16
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#endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_IPU_H */
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