forked from Minki/linux
18656782a8
These are changes for drivers that are intimately tied to some SoC and for some reason could not get merged through the respective subsystem maintainer tree. This time around, much of this is for at91, with the bulk of it being syscon and udc drivers. Also, there's: - coupled cpuidle support for Samsung Exynos4210 - Renesas 73A0 common-clk work - of/platform changes to tear down DMA mappings on device destruction - a few updates to the TI Keystone knav code -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJU4upSAAoJEIwa5zzehBx3HkUP/Rc4B1yZChNIFNfVq4dbei6w dT9WdFmxOIj2JLeXEypFBiNf1nSHmsxrZe9/IDACz2fYQOnaZZ6/786utUJP/PtC 2GDJy9cjL2Xh03We3nQp5z6J33XvpEni1t82cOpCl8wLBOQNnkjEks8UvLgi1LHW CNLcMm8JtDQ2aB/gRTjzetp9liZluESY5+Mig+loE2F/rzbMbNQDcWDDgUPyIQIS 1onL+Bad3BnGFdo/+qnkurGc81pxoKiQJty06VWFftzvIwxXhsNjrqls2+KzstAx 0lLvW1tqaDhXvUBImRM8GgfbldZslsgoFVmgESS9MpPMBNENYrkAiQNvJUnM7kd9 qHDQNq+zRNsz/k4fVvp/YUp7xEiAo4rLcFmp/dBr535jS2LNyiZnB94q+kXsin/m tiyEMx+RWxEHTEHN9WdKE61Ty1RbzOa5UTLSzOKFAkF+m2nvuQsJvb97n19coAq9 SSsj/wJgesfqrDEegphCDh1fyVxUzlAjjhTAyvPS155WvPzkbxZxuBbSqRuriRKA 2aCfVne2ELimHAr3LEPgPW2kFBcONHckOGe6MvrTX4zPHU8bb9WIeg+iGdQChnr3 nclT9jq+ZnQro5XTgUtPtadq100oEXlJbqpAzhd+cJbvgzSNbcWfcgE6kOWqd9uK oeWQWFLCdXLmXf9zCwmk =T7R2 -----END PGP SIGNATURE----- Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Olof Johansson: "These are changes for drivers that are intimately tied to some SoC and for some reason could not get merged through the respective subsystem maintainer tree. This time around, much of this is for at91, with the bulk of it being syscon and udc drivers. Also, there's: - coupled cpuidle support for Samsung Exynos4210 - Renesas 73A0 common-clk work - of/platform changes to tear down DMA mappings on device destruction - a few updates to the TI Keystone knav code" * tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits) cpuidle: exynos: add coupled cpuidle support for exynos4210 ARM: EXYNOS: apply S5P_CENTRAL_SEQ_OPTION fix only when necessary soc: ti: knav_qmss_queue: change knav_range_setup_acc_irq to static soc: ti: knav_qmss_queue: makefile tweak to build as dynamic module pcmcia: at91_cf: depend on !ARCH_MULTIPLATFORM soc: ti: knav_qmss_queue: export API calls for use by user driver of/platform: teardown DMA mappings on device destruction usb: gadget: at91_udc: Allocate udc instance usb: gadget: at91_udc: Update DT binding documentation usb: gadget: at91_udc: Rework for multi-platform kernel support usb: gadget: at91_udc: Simplify probe and remove functions usb: gadget: at91_udc: Remove non-DT handling code usb: gadget: at91_udc: Document DT clocks and clock-names property usb: gadget: at91_udc: Drop uclk clock usb: gadget: at91_udc: Fix clock names mfd: syscon: Add Atmel SMC binding doc mfd: syscon: Add atmel-smc registers definition mfd: syscon: Add Atmel Matrix bus DT binding documentation mfd: syscon: Add atmel-matrix registers definition clk: shmobile: fix sparse NULL pointer warning ...
305 lines
6.4 KiB
C
305 lines
6.4 KiB
C
/*
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* Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS - Power Management support
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*
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* Based on arch/arm/mach-s3c2410/pm.c
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/cpu_pm.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <asm/firmware.h>
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#include <asm/smp_scu.h>
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#include <asm/suspend.h>
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#include <mach/map.h>
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#include <plat/pm-common.h>
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#include "common.h"
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#include "exynos-pmu.h"
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#include "regs-pmu.h"
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static inline void __iomem *exynos_boot_vector_addr(void)
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{
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if (samsung_rev() == EXYNOS4210_REV_1_1)
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return pmu_base_addr + S5P_INFORM7;
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else if (samsung_rev() == EXYNOS4210_REV_1_0)
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return sysram_base_addr + 0x24;
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return pmu_base_addr + S5P_INFORM0;
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}
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static inline void __iomem *exynos_boot_vector_flag(void)
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{
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if (samsung_rev() == EXYNOS4210_REV_1_1)
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return pmu_base_addr + S5P_INFORM6;
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else if (samsung_rev() == EXYNOS4210_REV_1_0)
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return sysram_base_addr + 0x20;
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return pmu_base_addr + S5P_INFORM1;
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}
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#define S5P_CHECK_AFTR 0xFCBA0D10
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/* For Cortex-A9 Diagnostic and Power control register */
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static unsigned int save_arm_register[2];
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void exynos_cpu_save_register(void)
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{
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unsigned long tmp;
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/* Save Power control register */
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asm ("mrc p15, 0, %0, c15, c0, 0"
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: "=r" (tmp) : : "cc");
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save_arm_register[0] = tmp;
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/* Save Diagnostic register */
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asm ("mrc p15, 0, %0, c15, c0, 1"
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: "=r" (tmp) : : "cc");
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save_arm_register[1] = tmp;
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}
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void exynos_cpu_restore_register(void)
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{
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unsigned long tmp;
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/* Restore Power control register */
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tmp = save_arm_register[0];
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asm volatile ("mcr p15, 0, %0, c15, c0, 0"
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: : "r" (tmp)
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: "cc");
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/* Restore Diagnostic register */
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tmp = save_arm_register[1];
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asm volatile ("mcr p15, 0, %0, c15, c0, 1"
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: : "r" (tmp)
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: "cc");
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}
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void exynos_pm_central_suspend(void)
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{
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unsigned long tmp;
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/* Setting Central Sequence Register for power down mode */
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tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
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tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
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pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
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}
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int exynos_pm_central_resume(void)
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{
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unsigned long tmp;
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/*
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* If PMU failed while entering sleep mode, WFI will be
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* ignored by PMU and then exiting cpu_do_idle().
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* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
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* in this situation.
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*/
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tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
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if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
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tmp |= S5P_CENTRAL_LOWPWR_CFG;
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pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
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/* clear the wakeup state register */
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pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
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/* No need to perform below restore code */
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return -1;
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}
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return 0;
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}
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/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
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static void exynos_set_wakeupmask(long mask)
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{
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pmu_raw_writel(mask, S5P_WAKEUP_MASK);
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}
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static void exynos_cpu_set_boot_vector(long flags)
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{
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__raw_writel(virt_to_phys(exynos_cpu_resume),
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exynos_boot_vector_addr());
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__raw_writel(flags, exynos_boot_vector_flag());
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}
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static int exynos_aftr_finisher(unsigned long flags)
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{
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int ret;
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exynos_set_wakeupmask(0x0000ff3e);
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/* Set value of power down register for aftr mode */
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exynos_sys_powerdown_conf(SYS_AFTR);
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ret = call_firmware_op(do_idle, FW_DO_IDLE_AFTR);
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if (ret == -ENOSYS) {
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
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exynos_cpu_save_register();
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exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
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cpu_do_idle();
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}
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return 1;
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}
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void exynos_enter_aftr(void)
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{
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cpu_pm_enter();
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exynos_pm_central_suspend();
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if (of_machine_is_compatible("samsung,exynos4212") ||
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of_machine_is_compatible("samsung,exynos4412")) {
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/* Setting SEQ_OPTION register */
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pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
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S5P_CENTRAL_SEQ_OPTION);
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}
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cpu_suspend(0, exynos_aftr_finisher);
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
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scu_enable(S5P_VA_SCU);
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if (call_firmware_op(resume) == -ENOSYS)
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exynos_cpu_restore_register();
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}
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exynos_pm_central_resume();
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cpu_pm_exit();
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}
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static atomic_t cpu1_wakeup = ATOMIC_INIT(0);
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static int exynos_cpu0_enter_aftr(void)
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{
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int ret = -1;
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/*
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* If the other cpu is powered on, we have to power it off, because
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* the AFTR state won't work otherwise
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*/
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if (cpu_online(1)) {
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/*
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* We reach a sync point with the coupled idle state, we know
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* the other cpu will power down itself or will abort the
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* sequence, let's wait for one of these to happen
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*/
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while (exynos_cpu_power_state(1)) {
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/*
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* The other cpu may skip idle and boot back
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* up again
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*/
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if (atomic_read(&cpu1_wakeup))
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goto abort;
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/*
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* The other cpu may bounce through idle and
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* boot back up again, getting stuck in the
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* boot rom code
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*/
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if (__raw_readl(cpu_boot_reg_base()) == 0)
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goto abort;
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cpu_relax();
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}
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}
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exynos_enter_aftr();
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ret = 0;
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abort:
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if (cpu_online(1)) {
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/*
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* Set the boot vector to something non-zero
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*/
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__raw_writel(virt_to_phys(exynos_cpu_resume),
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cpu_boot_reg_base());
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dsb();
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/*
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* Turn on cpu1 and wait for it to be on
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*/
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exynos_cpu_power_up(1);
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while (exynos_cpu_power_state(1) != S5P_CORE_LOCAL_PWR_EN)
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cpu_relax();
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while (!atomic_read(&cpu1_wakeup)) {
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/*
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* Poke cpu1 out of the boot rom
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*/
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__raw_writel(virt_to_phys(exynos_cpu_resume),
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cpu_boot_reg_base());
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arch_send_wakeup_ipi_mask(cpumask_of(1));
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}
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}
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return ret;
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}
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static int exynos_wfi_finisher(unsigned long flags)
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{
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cpu_do_idle();
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return -1;
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}
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static int exynos_cpu1_powerdown(void)
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{
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int ret = -1;
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/*
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* Idle sequence for cpu1
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*/
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if (cpu_pm_enter())
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goto cpu1_aborted;
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/*
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* Turn off cpu 1
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*/
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exynos_cpu_power_down(1);
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ret = cpu_suspend(0, exynos_wfi_finisher);
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cpu_pm_exit();
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cpu1_aborted:
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dsb();
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/*
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* Notify cpu 0 that cpu 1 is awake
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*/
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atomic_set(&cpu1_wakeup, 1);
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return ret;
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}
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static void exynos_pre_enter_aftr(void)
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{
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__raw_writel(virt_to_phys(exynos_cpu_resume), cpu_boot_reg_base());
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}
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static void exynos_post_enter_aftr(void)
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{
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atomic_set(&cpu1_wakeup, 0);
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}
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struct cpuidle_exynos_data cpuidle_coupled_exynos_data = {
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.cpu0_enter_aftr = exynos_cpu0_enter_aftr,
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.cpu1_powerdown = exynos_cpu1_powerdown,
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.pre_enter_aftr = exynos_pre_enter_aftr,
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.post_enter_aftr = exynos_post_enter_aftr,
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};
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