forked from Minki/linux
0cacaf51a0
Two fixes are queued up. The first is an additional fix for the OMAP initialization order issue and the second patch fixes a possible section mismatch which can lead to a kernel crash in the AMD IOMMU driver when suspend/resume is used and the compiler has not inlined the iommu_set_device_table function. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJPWgA/AAoJECvwRC2XARrj7voQAN6evWicqjRDiXQgEC3muQFU OrA/Jz/i7+pHEYXcsTt0xHLb8juZNJAdkJjToB+oz7i/7D+TYRmJe+QRNkVmw7Ld d3DbUSUi9B3agvGblosKV3DYM8By1vTn9Gy2GNatW1yPuo5o4FHK2ePC5sn8Z/8z qwTZZnmvqluz7frNiw6Y3bNOqLd46z+9thUOoKmRn/fo3vKCOOVvb85yu1m/uqy6 Dmpn6ep0w53jK29ZTKWcL8PW0YrLTEfszhMcVshFT+Y7GVSGnSxwgSh1fnZm/WL6 z11L57dI0+7RS/z+cw+ko7ymIloV2v4ABRArMPIoLgbIQT0lidDNSqOQnPvWaBek MwdLL8W64lt2h4T7bLhDNRSDggWCX+EJYlk87O4hJYt4n57c3yT55z2+BGdoFivZ tzPshNWN4KVDMZCU6sTvzvz6eErwvro5wlVM2WxDVfXTxn6UTblP5uIQDGb2zVA9 G95kK/OlK/s+giwOSOKxtR62livKEAuJ2Croa5LsdJnLdCo6ipvIz9cuAG6eij2W tulJQUN3FZr288iUAOPQ9xj6hWYM9RXqoYBxAHAvgYgGuirj9E6hjk/fL0y6XGQk jcg0bCdJjh2RzsLZR0eeslybtlrvUsBWYCPYCAAmRjUYHwZ6s822aO7qh0VnrFuQ csH09+3B0twvJ+ZRJibN =PZDd -----END PGP SIGNATURE----- Merge tag 'iommu-fixes-v3.3-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull two IOMMU fixes from Joerg Roedel: "The first is an additional fix for the OMAP initialization order issue and the second patch fixes a possible section mismatch which can lead to a kernel crash in the AMD IOMMU driver when suspend/resume is used and the compiler has not inlined the iommu_set_device_table function." * tag 'iommu-fixes-v3.3-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: x86/amd: iommu_set_device_table() must not be __init ARM: OMAP: fix iommu, not mailbox
431 lines
10 KiB
C
431 lines
10 KiB
C
/*
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* Mailbox reservation modules for OMAP2/3
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*
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* Copyright (C) 2006-2009 Nokia Corporation
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* Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
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* and Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/pm_runtime.h>
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#include <plat/mailbox.h>
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#include <mach/irqs.h>
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#define MAILBOX_REVISION 0x000
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#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
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#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
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#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
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#define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
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#define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
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#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 10 * (u))
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#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 10 * (u))
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#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 10 * (u))
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#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
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#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
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#define MBOX_REG_SIZE 0x120
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#define OMAP4_MBOX_REG_SIZE 0x130
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#define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
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#define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
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static void __iomem *mbox_base;
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struct omap_mbox2_fifo {
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unsigned long msg;
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unsigned long fifo_stat;
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unsigned long msg_stat;
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};
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struct omap_mbox2_priv {
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struct omap_mbox2_fifo tx_fifo;
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struct omap_mbox2_fifo rx_fifo;
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unsigned long irqenable;
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unsigned long irqstatus;
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u32 newmsg_bit;
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u32 notfull_bit;
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u32 ctx[OMAP4_MBOX_NR_REGS];
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unsigned long irqdisable;
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};
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static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
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omap_mbox_type_t irq);
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static inline unsigned int mbox_read_reg(size_t ofs)
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{
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return __raw_readl(mbox_base + ofs);
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}
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static inline void mbox_write_reg(u32 val, size_t ofs)
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{
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__raw_writel(val, mbox_base + ofs);
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}
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/* Mailbox H/W preparations */
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static int omap2_mbox_startup(struct omap_mbox *mbox)
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{
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u32 l;
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pm_runtime_enable(mbox->dev->parent);
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pm_runtime_get_sync(mbox->dev->parent);
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l = mbox_read_reg(MAILBOX_REVISION);
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pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
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omap2_mbox_enable_irq(mbox, IRQ_RX);
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return 0;
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}
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static void omap2_mbox_shutdown(struct omap_mbox *mbox)
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{
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pm_runtime_put_sync(mbox->dev->parent);
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pm_runtime_disable(mbox->dev->parent);
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}
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/* Mailbox FIFO handle functions */
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static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
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{
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struct omap_mbox2_fifo *fifo =
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&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
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return (mbox_msg_t) mbox_read_reg(fifo->msg);
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}
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static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
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{
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struct omap_mbox2_fifo *fifo =
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&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
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mbox_write_reg(msg, fifo->msg);
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}
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static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
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{
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struct omap_mbox2_fifo *fifo =
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&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
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return (mbox_read_reg(fifo->msg_stat) == 0);
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}
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static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
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{
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struct omap_mbox2_fifo *fifo =
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&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
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return mbox_read_reg(fifo->fifo_stat);
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}
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/* Mailbox IRQ handle functions */
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static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
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omap_mbox_type_t irq)
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{
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struct omap_mbox2_priv *p = mbox->priv;
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u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
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l = mbox_read_reg(p->irqenable);
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l |= bit;
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mbox_write_reg(l, p->irqenable);
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}
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static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
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omap_mbox_type_t irq)
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{
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struct omap_mbox2_priv *p = mbox->priv;
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u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
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if (!cpu_is_omap44xx())
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bit = mbox_read_reg(p->irqdisable) & ~bit;
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mbox_write_reg(bit, p->irqdisable);
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}
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static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
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omap_mbox_type_t irq)
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{
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struct omap_mbox2_priv *p = mbox->priv;
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u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
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mbox_write_reg(bit, p->irqstatus);
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/* Flush posted write for irq status to avoid spurious interrupts */
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mbox_read_reg(p->irqstatus);
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}
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static int omap2_mbox_is_irq(struct omap_mbox *mbox,
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omap_mbox_type_t irq)
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{
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struct omap_mbox2_priv *p = mbox->priv;
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u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
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u32 enable = mbox_read_reg(p->irqenable);
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u32 status = mbox_read_reg(p->irqstatus);
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return (int)(enable & status & bit);
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}
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static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
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{
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int i;
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struct omap_mbox2_priv *p = mbox->priv;
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int nr_regs;
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if (cpu_is_omap44xx())
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nr_regs = OMAP4_MBOX_NR_REGS;
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else
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nr_regs = MBOX_NR_REGS;
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for (i = 0; i < nr_regs; i++) {
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p->ctx[i] = mbox_read_reg(i * sizeof(u32));
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dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
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i, p->ctx[i]);
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}
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}
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static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
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{
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int i;
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struct omap_mbox2_priv *p = mbox->priv;
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int nr_regs;
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if (cpu_is_omap44xx())
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nr_regs = OMAP4_MBOX_NR_REGS;
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else
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nr_regs = MBOX_NR_REGS;
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for (i = 0; i < nr_regs; i++) {
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mbox_write_reg(p->ctx[i], i * sizeof(u32));
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dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
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i, p->ctx[i]);
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}
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}
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static struct omap_mbox_ops omap2_mbox_ops = {
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.type = OMAP_MBOX_TYPE2,
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.startup = omap2_mbox_startup,
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.shutdown = omap2_mbox_shutdown,
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.fifo_read = omap2_mbox_fifo_read,
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.fifo_write = omap2_mbox_fifo_write,
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.fifo_empty = omap2_mbox_fifo_empty,
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.fifo_full = omap2_mbox_fifo_full,
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.enable_irq = omap2_mbox_enable_irq,
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.disable_irq = omap2_mbox_disable_irq,
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.ack_irq = omap2_mbox_ack_irq,
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.is_irq = omap2_mbox_is_irq,
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.save_ctx = omap2_mbox_save_ctx,
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.restore_ctx = omap2_mbox_restore_ctx,
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};
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/*
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* MAILBOX 0: ARM -> DSP,
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* MAILBOX 1: ARM <- DSP.
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* MAILBOX 2: ARM -> IVA,
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* MAILBOX 3: ARM <- IVA.
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*/
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/* FIXME: the following structs should be filled automatically by the user id */
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#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
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/* DSP */
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static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
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.tx_fifo = {
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.msg = MAILBOX_MESSAGE(0),
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.fifo_stat = MAILBOX_FIFOSTATUS(0),
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},
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.rx_fifo = {
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.msg = MAILBOX_MESSAGE(1),
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.msg_stat = MAILBOX_MSGSTATUS(1),
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},
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.irqenable = MAILBOX_IRQENABLE(0),
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.irqstatus = MAILBOX_IRQSTATUS(0),
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.notfull_bit = MAILBOX_IRQ_NOTFULL(0),
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.newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
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.irqdisable = MAILBOX_IRQENABLE(0),
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};
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struct omap_mbox mbox_dsp_info = {
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.name = "dsp",
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.ops = &omap2_mbox_ops,
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.priv = &omap2_mbox_dsp_priv,
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};
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#endif
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#if defined(CONFIG_ARCH_OMAP3)
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struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
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#endif
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#if defined(CONFIG_SOC_OMAP2420)
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/* IVA */
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static struct omap_mbox2_priv omap2_mbox_iva_priv = {
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.tx_fifo = {
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.msg = MAILBOX_MESSAGE(2),
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.fifo_stat = MAILBOX_FIFOSTATUS(2),
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},
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.rx_fifo = {
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.msg = MAILBOX_MESSAGE(3),
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.msg_stat = MAILBOX_MSGSTATUS(3),
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},
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.irqenable = MAILBOX_IRQENABLE(3),
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.irqstatus = MAILBOX_IRQSTATUS(3),
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.notfull_bit = MAILBOX_IRQ_NOTFULL(2),
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.newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
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.irqdisable = MAILBOX_IRQENABLE(3),
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};
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static struct omap_mbox mbox_iva_info = {
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.name = "iva",
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.ops = &omap2_mbox_ops,
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.priv = &omap2_mbox_iva_priv,
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};
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#endif
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#ifdef CONFIG_ARCH_OMAP2
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struct omap_mbox *omap2_mboxes[] = {
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&mbox_dsp_info,
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#ifdef CONFIG_SOC_OMAP2420
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&mbox_iva_info,
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#endif
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NULL
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};
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#endif
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#if defined(CONFIG_ARCH_OMAP4)
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/* OMAP4 */
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static struct omap_mbox2_priv omap2_mbox_1_priv = {
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.tx_fifo = {
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.msg = MAILBOX_MESSAGE(0),
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.fifo_stat = MAILBOX_FIFOSTATUS(0),
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},
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.rx_fifo = {
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.msg = MAILBOX_MESSAGE(1),
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.msg_stat = MAILBOX_MSGSTATUS(1),
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},
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.irqenable = OMAP4_MAILBOX_IRQENABLE(0),
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.irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
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.notfull_bit = MAILBOX_IRQ_NOTFULL(0),
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.newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
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.irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
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};
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struct omap_mbox mbox_1_info = {
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.name = "mailbox-1",
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.ops = &omap2_mbox_ops,
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.priv = &omap2_mbox_1_priv,
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};
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static struct omap_mbox2_priv omap2_mbox_2_priv = {
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.tx_fifo = {
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.msg = MAILBOX_MESSAGE(3),
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.fifo_stat = MAILBOX_FIFOSTATUS(3),
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},
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.rx_fifo = {
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.msg = MAILBOX_MESSAGE(2),
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.msg_stat = MAILBOX_MSGSTATUS(2),
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},
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.irqenable = OMAP4_MAILBOX_IRQENABLE(0),
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.irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
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.notfull_bit = MAILBOX_IRQ_NOTFULL(3),
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.newmsg_bit = MAILBOX_IRQ_NEWMSG(2),
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.irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
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};
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struct omap_mbox mbox_2_info = {
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.name = "mailbox-2",
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.ops = &omap2_mbox_ops,
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.priv = &omap2_mbox_2_priv,
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};
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struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
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#endif
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static int __devinit omap2_mbox_probe(struct platform_device *pdev)
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{
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struct resource *mem;
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int ret;
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struct omap_mbox **list;
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if (false)
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;
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#if defined(CONFIG_ARCH_OMAP3)
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else if (cpu_is_omap34xx()) {
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list = omap3_mboxes;
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list[0]->irq = platform_get_irq(pdev, 0);
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}
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#endif
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#if defined(CONFIG_ARCH_OMAP2)
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else if (cpu_is_omap2430()) {
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list = omap2_mboxes;
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list[0]->irq = platform_get_irq(pdev, 0);
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} else if (cpu_is_omap2420()) {
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list = omap2_mboxes;
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list[0]->irq = platform_get_irq_byname(pdev, "dsp");
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list[1]->irq = platform_get_irq_byname(pdev, "iva");
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}
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#endif
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#if defined(CONFIG_ARCH_OMAP4)
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else if (cpu_is_omap44xx()) {
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list = omap4_mboxes;
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list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
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}
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#endif
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else {
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pr_err("%s: platform not supported\n", __func__);
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return -ENODEV;
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}
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mbox_base = ioremap(mem->start, resource_size(mem));
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if (!mbox_base)
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return -ENOMEM;
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ret = omap_mbox_register(&pdev->dev, list);
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if (ret) {
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iounmap(mbox_base);
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return ret;
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}
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return 0;
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}
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static int __devexit omap2_mbox_remove(struct platform_device *pdev)
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{
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omap_mbox_unregister();
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iounmap(mbox_base);
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return 0;
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}
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static struct platform_driver omap2_mbox_driver = {
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.probe = omap2_mbox_probe,
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.remove = __devexit_p(omap2_mbox_remove),
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.driver = {
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.name = "omap-mailbox",
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},
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};
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static int __init omap2_mbox_init(void)
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{
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return platform_driver_register(&omap2_mbox_driver);
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}
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static void __exit omap2_mbox_exit(void)
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{
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platform_driver_unregister(&omap2_mbox_driver);
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}
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module_init(omap2_mbox_init);
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module_exit(omap2_mbox_exit);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
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MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
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MODULE_AUTHOR("Paul Mundt");
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MODULE_ALIAS("platform:omap2-mailbox");
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