Joerg Roedel 29dcc60f6a x86/boot/compressed/64: Add stage1 #VC handler ... Add the first handler for #VC exceptions. At stage 1 there is no GHCB yet because the kernel might still be running on the EFI page table. The stage 1 handler is limited to the MSR-based protocol to talk to the hypervisor and can only support CPUID exit-codes, but that is enough to get to stage 2. [ bp: Zap superfluous newlines after rd/wrmsr instruction mnemonics. ] Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200907131613.12703-20-joro@8bytes.org		2020-09-07 19:45:25 +02:00
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asm	x86/boot/compressed/64: Add stage1 #VC handler	2020-09-07 19:45:25 +02:00
uapi/asm	Support for FSGSBASE. Almost 5 years after the first RFC to support it,	2020-08-04 21:16:22 -07:00