ab4bec16d4
Some newer boards with these chipsets aren't compatible with the prior version of the SEC2 FW, and fail to load as a result. This newer FW is actually the one we already use on >=GP108. Unfortunately, there are interface differences in GP108's FW, making it impossible to simply move files around in linux-firmware to solve this. We need to be able to keep compatibility with all linux-firmware/kernel combinations, which means supporting both firmwares. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
72 lines
3.1 KiB
C
72 lines
3.1 KiB
C
/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __NVKM_SECBOOT_ACR_R361_H__
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#define __NVKM_SECBOOT_ACR_R361_H__
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#include "acr_r352.h"
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/**
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* struct acr_r361_flcn_bl_desc - DMEM bootloader descriptor
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* @signature: 16B signature for secure code. 0s if no secure code
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* @ctx_dma: DMA context to be used by BL while loading code/data
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* @code_dma_base: 256B-aligned Physical FB Address where code is located
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* (falcon's $xcbase register)
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* @non_sec_code_off: offset from code_dma_base where the non-secure code is
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* located. The offset must be multiple of 256 to help perf
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* @non_sec_code_size: the size of the nonSecure code part.
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* @sec_code_off: offset from code_dma_base where the secure code is
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* located. The offset must be multiple of 256 to help perf
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* @sec_code_size: offset from code_dma_base where the secure code is
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* located. The offset must be multiple of 256 to help perf
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* @code_entry_point: code entry point which will be invoked by BL after
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* code is loaded.
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* @data_dma_base: 256B aligned Physical FB Address where data is located.
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* (falcon's $xdbase register)
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* @data_size: size of data block. Should be multiple of 256B
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*
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* Structure used by the bootloader to load the rest of the code. This has
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* to be filled by host and copied into DMEM at offset provided in the
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* hsflcn_bl_desc.bl_desc_dmem_load_off.
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*/
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struct acr_r361_flcn_bl_desc {
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u32 reserved[4];
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u32 signature[4];
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u32 ctx_dma;
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struct flcn_u64 code_dma_base;
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u32 non_sec_code_off;
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u32 non_sec_code_size;
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u32 sec_code_off;
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u32 sec_code_size;
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u32 code_entry_point;
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struct flcn_u64 data_dma_base;
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u32 data_size;
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};
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void acr_r361_generate_hs_bl_desc(const struct hsf_load_header *, void *, u64);
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extern const struct acr_r352_ls_func acr_r361_ls_fecs_func;
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extern const struct acr_r352_ls_func acr_r361_ls_gpccs_func;
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extern const struct acr_r352_ls_func acr_r361_ls_pmu_func;
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extern const struct acr_r352_lsf_func acr_r361_ls_sec2_func_0;
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#endif
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