afc3bca4cf
DT unit addresses should be lower case hex. Fix all the
binding examples.
Converted with the following command from Krzysztof Kozlowski:
sed -e 's/@\([a-fA-F0-9_-]*\) {/@\L\1 {/' -i $(find Documentation/devicetree/bindings -name '*.txt')
Signed-off-by: Rob Herring <robh@kernel.org>
211 lines
6.5 KiB
Plaintext
211 lines
6.5 KiB
Plaintext
* Device tree bindings for Texas instruments AEMIF controller
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The Async External Memory Interface (EMIF16/AEMIF) controller is intended to
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provide a glue-less interface to a variety of asynchronous memory devices like
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ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories
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can be accessed at any given time via four chip selects with 64M byte access
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per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM
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and Mobile SDR are not supported.
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Documentation:
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Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
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OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
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Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
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Required properties:
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- compatible: "ti,davinci-aemif"
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"ti,keystone-aemif"
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"ti,da850-aemif"
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- reg: contains offset/length value for AEMIF control registers
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space.
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- #address-cells: Must be 2. The partition number has to be encoded in the
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first address cell and it may accept values 0..N-1
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(N - total number of partitions). It's recommended to
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assign N-1 number for the control partition. The second
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cell is the offset into the partition.
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- #size-cells: Must be set to 1.
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- ranges: Contains memory regions. There are two types of
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ranges/partitions:
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- CS-specific partition/range. If continuous, must be
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set up to reflect the memory layout for 4 chipselects,
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if not then additional range/partition can be added and
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child device can select the proper one.
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- control partition which is common for all CS
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interfaces.
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- clocks: the clock feeding the controller clock. Required only
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if clock tree data present in device tree.
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See clock-bindings.txt
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- clock-names: clock name. It has to be "aemif". Required only if clock
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tree data present in device tree, in another case don't
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use it.
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See clock-bindings.txt
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- clock-ranges: Empty property indicating that child nodes can inherit
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named clocks. Required only if clock tree data present
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in device tree.
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See clock-bindings.txt
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Child chip-select (cs) nodes contain the memory devices nodes connected to
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such as NOR (e.g. cfi-flash) and NAND (ti,davinci-nand, see davinci-nand.txt).
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There might be board specific devices like FPGAs.
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Required child cs node properties:
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- #address-cells: Must be 2.
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- #size-cells: Must be 1.
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- ranges: Empty property indicating that child nodes can inherit
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memory layout.
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- clock-ranges: Empty property indicating that child nodes can inherit
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named clocks. Required only if clock tree data present
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in device tree.
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- ti,cs-chipselect: number of chipselect. Indicates on the aemif driver
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which chipselect is used for accessing the memory. For
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compatibles "ti,davinci-aemif" and "ti,keystone-aemif"
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it can be in range [0-3]. For compatible
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"ti,da850-aemif" range is [2-5].
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Optional child cs node properties:
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- ti,cs-bus-width: width of the asynchronous device's data bus
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8 or 16 if not preset 8
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- ti,cs-select-strobe-mode: enable/disable select strobe mode
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In select strobe mode chip select behaves as
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the strobe and is active only during the strobe
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period. If present then enable.
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- ti,cs-extended-wait-mode: enable/disable extended wait mode
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if set, the controller monitors the EMIFWAIT pin
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mapped to that chip select to determine if the
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device wants to extend the strobe period. If
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present then enable.
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- ti,cs-min-turnaround-ns: minimum turn around time, ns
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Time between the end of one asynchronous memory
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access and the start of another asynchronous
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memory access. This delay is not incurred
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between a read followed by read or a write
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followed by a write to same chip select.
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- ti,cs-read-setup-ns: read setup width, ns
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Time between the beginning of a memory cycle
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and the activation of read strobe.
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Minimum value is 1 (0 treated as 1).
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- ti,cs-read-strobe-ns: read strobe width, ns
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Time between the activation and deactivation of
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the read strobe.
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Minimum value is 1 (0 treated as 1).
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- ti,cs-read-hold-ns: read hold width, ns
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Time between the deactivation of the read
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strobe and the end of the cycle (which may be
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either an address change or the deactivation of
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the chip select signal.
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Minimum value is 1 (0 treated as 1).
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- ti,cs-write-setup-ns: write setup width, ns
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Time between the beginning of a memory cycle
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and the activation of write strobe.
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Minimum value is 1 (0 treated as 1).
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- ti,cs-write-strobe-ns: write strobe width, ns
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Time between the activation and deactivation of
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the write strobe.
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Minimum value is 1 (0 treated as 1).
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- ti,cs-write-hold-ns: write hold width, ns
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Time between the deactivation of the write
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strobe and the end of the cycle (which may be
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either an address change or the deactivation of
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the chip select signal.
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Minimum value is 1 (0 treated as 1).
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If any of the above parameters are absent, current parameter value will be taken
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from the corresponding HW reg.
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Example for aemif, davinci nand and nor flash chip select shown below.
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memory-controller@21000a00 {
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compatible = "ti,davinci-aemif";
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#address-cells = <2>;
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#size-cells = <1>;
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clocks = <&clkaemif 0>;
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clock-names = "aemif";
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clock-ranges;
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reg = <0x21000A00 0x00000100>;
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ranges = <0 0 0x70000000 0x10000000
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1 0 0x21000A00 0x00000100>;
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/*
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* Partition0: CS-specific memory range which is
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* implemented as continuous physical memory region
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* Partition1: control memory range
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*/
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nand:cs2 {
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#address-cells = <2>;
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#size-cells = <1>;
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clock-ranges;
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ranges;
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ti,cs-chipselect = <2>;
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/* all timings in nanoseconds */
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ti,cs-min-turnaround-ns = <0>;
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ti,cs-read-hold-ns = <7>;
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ti,cs-read-strobe-ns = <42>;
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ti,cs-read-setup-ns = <14>;
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ti,cs-write-hold-ns = <7>;
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ti,cs-write-strobe-ns = <42>;
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ti,cs-write-setup-ns = <14>;
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nand@0,0x8000000 {
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compatible = "ti,davinci-nand";
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reg = <0 0x8000000 0x4000000
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1 0x0000000 0x0000100>;
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/*
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* Partition0, offset 0x8000000, size 0x4000000
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* Partition1, offset 0x0000000, size 0x0000100
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*/
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.. see davinci-nand.txt
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};
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};
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nor:cs0 {
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#address-cells = <2>;
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#size-cells = <1>;
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clock-ranges;
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ranges;
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ti,cs-chipselect = <0>;
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/* all timings in nanoseconds */
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ti,cs-min-turnaround-ns = <0>;
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ti,cs-read-hold-ns = <8>;
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ti,cs-read-strobe-ns = <40>;
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ti,cs-read-setup-ns = <14>;
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ti,cs-write-hold-ns = <7>;
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ti,cs-write-strobe-ns = <40>;
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ti,cs-write-setup-ns = <14>;
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ti,cs-bus-width = <16>;
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flash@0,0x0000000 {
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compatible = "cfi-flash";
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reg = <0 0x0000000 0x4000000>;
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...
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};
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};
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};
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