forked from Minki/linux
a2ec19f888
The assignment 'cf->data[2] |= CAN_ERR_PROT_UNSPEC' used at CAN error message creation time is obsolete as CAN_ERR_PROT_UNSPEC is zero and cf->data[2] is initialized with zero in alloc_can_err_skb() anyway. So we could either assign 'cf->data[2] = CAN_ERR_PROT_UNSPEC' correctly or we can remove the obsolete OR operation entirely. Signed-off-by: Oliver Hartkopp <socketcan@hartkopp.net> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
785 lines
19 KiB
C
785 lines
19 KiB
C
/*
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* Blackfin On-Chip CAN Driver
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*
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* Copyright 2004-2009 Analog Devices Inc.
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*
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* Enter bugs at http://blackfin.uclinux.org/
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/interrupt.h>
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#include <linux/errno.h>
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#include <linux/netdevice.h>
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#include <linux/skbuff.h>
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#include <linux/platform_device.h>
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#include <linux/can/dev.h>
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#include <linux/can/error.h>
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#include <asm/portmux.h>
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#define DRV_NAME "bfin_can"
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#define BFIN_CAN_TIMEOUT 100
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#define TX_ECHO_SKB_MAX 1
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/* transmit and receive channels */
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#define TRANSMIT_CHL 24
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#define RECEIVE_STD_CHL 0
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#define RECEIVE_EXT_CHL 4
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#define RECEIVE_RTR_CHL 8
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#define RECEIVE_EXT_RTR_CHL 12
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#define MAX_CHL_NUMBER 32
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/* All Blackfin system MMRs are padded to 32bits even if the register
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* itself is only 16bits. So use a helper macro to streamline this
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*/
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#define __BFP(m) u16 m; u16 __pad_##m
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/* bfin can registers layout */
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struct bfin_can_mask_regs {
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__BFP(aml);
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__BFP(amh);
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};
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struct bfin_can_channel_regs {
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/* data[0,2,4,6] -> data{0,1,2,3} while data[1,3,5,7] is padding */
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u16 data[8];
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__BFP(dlc);
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__BFP(tsv);
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__BFP(id0);
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__BFP(id1);
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};
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struct bfin_can_regs {
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/* global control and status registers */
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__BFP(mc1); /* offset 0x00 */
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__BFP(md1); /* offset 0x04 */
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__BFP(trs1); /* offset 0x08 */
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__BFP(trr1); /* offset 0x0c */
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__BFP(ta1); /* offset 0x10 */
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__BFP(aa1); /* offset 0x14 */
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__BFP(rmp1); /* offset 0x18 */
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__BFP(rml1); /* offset 0x1c */
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__BFP(mbtif1); /* offset 0x20 */
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__BFP(mbrif1); /* offset 0x24 */
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__BFP(mbim1); /* offset 0x28 */
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__BFP(rfh1); /* offset 0x2c */
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__BFP(opss1); /* offset 0x30 */
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u32 __pad1[3];
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__BFP(mc2); /* offset 0x40 */
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__BFP(md2); /* offset 0x44 */
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__BFP(trs2); /* offset 0x48 */
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__BFP(trr2); /* offset 0x4c */
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__BFP(ta2); /* offset 0x50 */
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__BFP(aa2); /* offset 0x54 */
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__BFP(rmp2); /* offset 0x58 */
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__BFP(rml2); /* offset 0x5c */
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__BFP(mbtif2); /* offset 0x60 */
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__BFP(mbrif2); /* offset 0x64 */
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__BFP(mbim2); /* offset 0x68 */
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__BFP(rfh2); /* offset 0x6c */
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__BFP(opss2); /* offset 0x70 */
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u32 __pad2[3];
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__BFP(clock); /* offset 0x80 */
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__BFP(timing); /* offset 0x84 */
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__BFP(debug); /* offset 0x88 */
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__BFP(status); /* offset 0x8c */
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__BFP(cec); /* offset 0x90 */
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__BFP(gis); /* offset 0x94 */
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__BFP(gim); /* offset 0x98 */
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__BFP(gif); /* offset 0x9c */
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__BFP(control); /* offset 0xa0 */
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__BFP(intr); /* offset 0xa4 */
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__BFP(version); /* offset 0xa8 */
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__BFP(mbtd); /* offset 0xac */
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__BFP(ewr); /* offset 0xb0 */
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__BFP(esr); /* offset 0xb4 */
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u32 __pad3[2];
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__BFP(ucreg); /* offset 0xc0 */
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__BFP(uccnt); /* offset 0xc4 */
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__BFP(ucrc); /* offset 0xc8 */
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__BFP(uccnf); /* offset 0xcc */
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u32 __pad4[1];
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__BFP(version2); /* offset 0xd4 */
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u32 __pad5[10];
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/* channel(mailbox) mask and message registers */
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struct bfin_can_mask_regs msk[MAX_CHL_NUMBER]; /* offset 0x100 */
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struct bfin_can_channel_regs chl[MAX_CHL_NUMBER]; /* offset 0x200 */
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};
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#undef __BFP
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#define SRS 0x0001 /* Software Reset */
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#define SER 0x0008 /* Stuff Error */
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#define BOIM 0x0008 /* Enable Bus Off Interrupt */
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#define CCR 0x0080 /* CAN Configuration Mode Request */
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#define CCA 0x0080 /* Configuration Mode Acknowledge */
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#define SAM 0x0080 /* Sampling */
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#define AME 0x8000 /* Acceptance Mask Enable */
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#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
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#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
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#define RTR 0x4000 /* Remote Frame Transmission Request */
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#define BOIS 0x0008 /* Bus Off IRQ Status */
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#define IDE 0x2000 /* Identifier Extension */
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#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
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#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
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#define EWTIS 0x0001 /* TX Error Count IRQ Status */
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#define EWRIS 0x0002 /* RX Error Count IRQ Status */
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#define BEF 0x0040 /* Bit Error Flag */
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#define FER 0x0080 /* Form Error Flag */
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#define SMR 0x0020 /* Sleep Mode Request */
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#define SMACK 0x0008 /* Sleep Mode Acknowledge */
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/*
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* bfin can private data
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*/
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struct bfin_can_priv {
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struct can_priv can; /* must be the first member */
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struct net_device *dev;
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void __iomem *membase;
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int rx_irq;
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int tx_irq;
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int err_irq;
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unsigned short *pin_list;
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};
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/*
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* bfin can timing parameters
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*/
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static const struct can_bittiming_const bfin_can_bittiming_const = {
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.name = DRV_NAME,
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.tseg1_min = 1,
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.tseg1_max = 16,
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.tseg2_min = 1,
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.tseg2_max = 8,
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.sjw_max = 4,
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/*
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* Although the BRP field can be set to any value, it is recommended
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* that the value be greater than or equal to 4, as restrictions
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* apply to the bit timing configuration when BRP is less than 4.
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*/
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.brp_min = 4,
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.brp_max = 1024,
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.brp_inc = 1,
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};
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static int bfin_can_set_bittiming(struct net_device *dev)
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{
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struct bfin_can_priv *priv = netdev_priv(dev);
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struct bfin_can_regs __iomem *reg = priv->membase;
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struct can_bittiming *bt = &priv->can.bittiming;
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u16 clk, timing;
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clk = bt->brp - 1;
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timing = ((bt->sjw - 1) << 8) | (bt->prop_seg + bt->phase_seg1 - 1) |
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((bt->phase_seg2 - 1) << 4);
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/*
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* If the SAM bit is set, the input signal is oversampled three times
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* at the SCLK rate.
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*/
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if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
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timing |= SAM;
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writew(clk, ®->clock);
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writew(timing, ®->timing);
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netdev_info(dev, "setting CLOCK=0x%04x TIMING=0x%04x\n", clk, timing);
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return 0;
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}
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static void bfin_can_set_reset_mode(struct net_device *dev)
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{
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struct bfin_can_priv *priv = netdev_priv(dev);
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struct bfin_can_regs __iomem *reg = priv->membase;
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int timeout = BFIN_CAN_TIMEOUT;
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int i;
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/* disable interrupts */
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writew(0, ®->mbim1);
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writew(0, ®->mbim2);
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writew(0, ®->gim);
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/* reset can and enter configuration mode */
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writew(SRS | CCR, ®->control);
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writew(CCR, ®->control);
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while (!(readw(®->control) & CCA)) {
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udelay(10);
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if (--timeout == 0) {
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netdev_err(dev, "fail to enter configuration mode\n");
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BUG();
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}
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}
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/*
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* All mailbox configurations are marked as inactive
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* by writing to CAN Mailbox Configuration Registers 1 and 2
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* For all bits: 0 - Mailbox disabled, 1 - Mailbox enabled
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*/
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writew(0, ®->mc1);
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writew(0, ®->mc2);
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/* Set Mailbox Direction */
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writew(0xFFFF, ®->md1); /* mailbox 1-16 are RX */
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writew(0, ®->md2); /* mailbox 17-32 are TX */
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/* RECEIVE_STD_CHL */
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for (i = 0; i < 2; i++) {
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writew(0, ®->chl[RECEIVE_STD_CHL + i].id0);
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writew(AME, ®->chl[RECEIVE_STD_CHL + i].id1);
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writew(0, ®->chl[RECEIVE_STD_CHL + i].dlc);
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writew(0x1FFF, ®->msk[RECEIVE_STD_CHL + i].amh);
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writew(0xFFFF, ®->msk[RECEIVE_STD_CHL + i].aml);
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}
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/* RECEIVE_EXT_CHL */
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for (i = 0; i < 2; i++) {
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writew(0, ®->chl[RECEIVE_EXT_CHL + i].id0);
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writew(AME | IDE, ®->chl[RECEIVE_EXT_CHL + i].id1);
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writew(0, ®->chl[RECEIVE_EXT_CHL + i].dlc);
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writew(0x1FFF, ®->msk[RECEIVE_EXT_CHL + i].amh);
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writew(0xFFFF, ®->msk[RECEIVE_EXT_CHL + i].aml);
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}
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writew(BIT(TRANSMIT_CHL - 16), ®->mc2);
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writew(BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL), ®->mc1);
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priv->can.state = CAN_STATE_STOPPED;
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}
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static void bfin_can_set_normal_mode(struct net_device *dev)
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{
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struct bfin_can_priv *priv = netdev_priv(dev);
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struct bfin_can_regs __iomem *reg = priv->membase;
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int timeout = BFIN_CAN_TIMEOUT;
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/*
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* leave configuration mode
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*/
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writew(readw(®->control) & ~CCR, ®->control);
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while (readw(®->status) & CCA) {
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udelay(10);
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if (--timeout == 0) {
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netdev_err(dev, "fail to leave configuration mode\n");
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BUG();
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}
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}
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/*
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* clear _All_ tx and rx interrupts
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*/
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writew(0xFFFF, ®->mbtif1);
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writew(0xFFFF, ®->mbtif2);
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writew(0xFFFF, ®->mbrif1);
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writew(0xFFFF, ®->mbrif2);
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/*
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* clear global interrupt status register
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*/
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writew(0x7FF, ®->gis); /* overwrites with '1' */
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/*
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* Initialize Interrupts
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* - set bits in the mailbox interrupt mask register
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* - global interrupt mask
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*/
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writew(BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL), ®->mbim1);
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writew(BIT(TRANSMIT_CHL - 16), ®->mbim2);
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writew(EPIM | BOIM | RMLIM, ®->gim);
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}
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static void bfin_can_start(struct net_device *dev)
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{
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struct bfin_can_priv *priv = netdev_priv(dev);
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/* enter reset mode */
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if (priv->can.state != CAN_STATE_STOPPED)
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bfin_can_set_reset_mode(dev);
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/* leave reset mode */
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bfin_can_set_normal_mode(dev);
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}
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static int bfin_can_set_mode(struct net_device *dev, enum can_mode mode)
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{
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switch (mode) {
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case CAN_MODE_START:
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bfin_can_start(dev);
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if (netif_queue_stopped(dev))
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netif_wake_queue(dev);
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break;
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default:
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return -EOPNOTSUPP;
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}
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return 0;
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}
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static int bfin_can_get_berr_counter(const struct net_device *dev,
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struct can_berr_counter *bec)
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{
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struct bfin_can_priv *priv = netdev_priv(dev);
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struct bfin_can_regs __iomem *reg = priv->membase;
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u16 cec = readw(®->cec);
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bec->txerr = cec >> 8;
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bec->rxerr = cec;
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return 0;
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}
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static int bfin_can_start_xmit(struct sk_buff *skb, struct net_device *dev)
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{
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struct bfin_can_priv *priv = netdev_priv(dev);
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struct bfin_can_regs __iomem *reg = priv->membase;
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struct can_frame *cf = (struct can_frame *)skb->data;
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u8 dlc = cf->can_dlc;
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canid_t id = cf->can_id;
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u8 *data = cf->data;
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u16 val;
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int i;
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if (can_dropped_invalid_skb(dev, skb))
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return NETDEV_TX_OK;
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netif_stop_queue(dev);
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/* fill id */
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if (id & CAN_EFF_FLAG) {
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writew(id, ®->chl[TRANSMIT_CHL].id0);
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val = ((id & 0x1FFF0000) >> 16) | IDE;
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} else
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val = (id << 2);
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if (id & CAN_RTR_FLAG)
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val |= RTR;
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writew(val | AME, ®->chl[TRANSMIT_CHL].id1);
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/* fill payload */
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for (i = 0; i < 8; i += 2) {
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val = ((7 - i) < dlc ? (data[7 - i]) : 0) +
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((6 - i) < dlc ? (data[6 - i] << 8) : 0);
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writew(val, ®->chl[TRANSMIT_CHL].data[i]);
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}
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/* fill data length code */
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writew(dlc, ®->chl[TRANSMIT_CHL].dlc);
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can_put_echo_skb(skb, dev, 0);
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/* set transmit request */
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writew(BIT(TRANSMIT_CHL - 16), ®->trs2);
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return 0;
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}
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static void bfin_can_rx(struct net_device *dev, u16 isrc)
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{
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struct bfin_can_priv *priv = netdev_priv(dev);
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struct net_device_stats *stats = &dev->stats;
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struct bfin_can_regs __iomem *reg = priv->membase;
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struct can_frame *cf;
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struct sk_buff *skb;
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int obj;
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int i;
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u16 val;
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skb = alloc_can_skb(dev, &cf);
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if (skb == NULL)
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return;
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/* get id */
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if (isrc & BIT(RECEIVE_EXT_CHL)) {
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/* extended frame format (EFF) */
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cf->can_id = ((readw(®->chl[RECEIVE_EXT_CHL].id1)
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& 0x1FFF) << 16)
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+ readw(®->chl[RECEIVE_EXT_CHL].id0);
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cf->can_id |= CAN_EFF_FLAG;
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obj = RECEIVE_EXT_CHL;
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} else {
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/* standard frame format (SFF) */
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cf->can_id = (readw(®->chl[RECEIVE_STD_CHL].id1)
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& 0x1ffc) >> 2;
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obj = RECEIVE_STD_CHL;
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}
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if (readw(®->chl[obj].id1) & RTR)
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cf->can_id |= CAN_RTR_FLAG;
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/* get data length code */
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cf->can_dlc = get_can_dlc(readw(®->chl[obj].dlc) & 0xF);
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/* get payload */
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for (i = 0; i < 8; i += 2) {
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val = readw(®->chl[obj].data[i]);
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cf->data[7 - i] = (7 - i) < cf->can_dlc ? val : 0;
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cf->data[6 - i] = (6 - i) < cf->can_dlc ? (val >> 8) : 0;
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}
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stats->rx_packets++;
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stats->rx_bytes += cf->can_dlc;
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netif_rx(skb);
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}
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static int bfin_can_err(struct net_device *dev, u16 isrc, u16 status)
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{
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struct bfin_can_priv *priv = netdev_priv(dev);
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struct bfin_can_regs __iomem *reg = priv->membase;
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struct net_device_stats *stats = &dev->stats;
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struct can_frame *cf;
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struct sk_buff *skb;
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enum can_state state = priv->can.state;
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skb = alloc_can_err_skb(dev, &cf);
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if (skb == NULL)
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return -ENOMEM;
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if (isrc & RMLIS) {
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/* data overrun interrupt */
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netdev_dbg(dev, "data overrun interrupt\n");
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cf->can_id |= CAN_ERR_CRTL;
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cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
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stats->rx_over_errors++;
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stats->rx_errors++;
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}
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if (isrc & BOIS) {
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netdev_dbg(dev, "bus-off mode interrupt\n");
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state = CAN_STATE_BUS_OFF;
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cf->can_id |= CAN_ERR_BUSOFF;
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priv->can.can_stats.bus_off++;
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can_bus_off(dev);
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}
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if (isrc & EPIS) {
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/* error passive interrupt */
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netdev_dbg(dev, "error passive interrupt\n");
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state = CAN_STATE_ERROR_PASSIVE;
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}
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if ((isrc & EWTIS) || (isrc & EWRIS)) {
|
|
netdev_dbg(dev, "Error Warning Transmit/Receive Interrupt\n");
|
|
state = CAN_STATE_ERROR_WARNING;
|
|
}
|
|
|
|
if (state != priv->can.state && (state == CAN_STATE_ERROR_WARNING ||
|
|
state == CAN_STATE_ERROR_PASSIVE)) {
|
|
u16 cec = readw(®->cec);
|
|
u8 rxerr = cec;
|
|
u8 txerr = cec >> 8;
|
|
|
|
cf->can_id |= CAN_ERR_CRTL;
|
|
if (state == CAN_STATE_ERROR_WARNING) {
|
|
priv->can.can_stats.error_warning++;
|
|
cf->data[1] = (txerr > rxerr) ?
|
|
CAN_ERR_CRTL_TX_WARNING :
|
|
CAN_ERR_CRTL_RX_WARNING;
|
|
} else {
|
|
priv->can.can_stats.error_passive++;
|
|
cf->data[1] = (txerr > rxerr) ?
|
|
CAN_ERR_CRTL_TX_PASSIVE :
|
|
CAN_ERR_CRTL_RX_PASSIVE;
|
|
}
|
|
}
|
|
|
|
if (status) {
|
|
priv->can.can_stats.bus_error++;
|
|
|
|
cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
|
|
|
|
if (status & BEF)
|
|
cf->data[2] |= CAN_ERR_PROT_BIT;
|
|
else if (status & FER)
|
|
cf->data[2] |= CAN_ERR_PROT_FORM;
|
|
else if (status & SER)
|
|
cf->data[2] |= CAN_ERR_PROT_STUFF;
|
|
}
|
|
|
|
priv->can.state = state;
|
|
|
|
stats->rx_packets++;
|
|
stats->rx_bytes += cf->can_dlc;
|
|
netif_rx(skb);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static irqreturn_t bfin_can_interrupt(int irq, void *dev_id)
|
|
{
|
|
struct net_device *dev = dev_id;
|
|
struct bfin_can_priv *priv = netdev_priv(dev);
|
|
struct bfin_can_regs __iomem *reg = priv->membase;
|
|
struct net_device_stats *stats = &dev->stats;
|
|
u16 status, isrc;
|
|
|
|
if ((irq == priv->tx_irq) && readw(®->mbtif2)) {
|
|
/* transmission complete interrupt */
|
|
writew(0xFFFF, ®->mbtif2);
|
|
stats->tx_packets++;
|
|
stats->tx_bytes += readw(®->chl[TRANSMIT_CHL].dlc);
|
|
can_get_echo_skb(dev, 0);
|
|
netif_wake_queue(dev);
|
|
} else if ((irq == priv->rx_irq) && readw(®->mbrif1)) {
|
|
/* receive interrupt */
|
|
isrc = readw(®->mbrif1);
|
|
writew(0xFFFF, ®->mbrif1);
|
|
bfin_can_rx(dev, isrc);
|
|
} else if ((irq == priv->err_irq) && readw(®->gis)) {
|
|
/* error interrupt */
|
|
isrc = readw(®->gis);
|
|
status = readw(®->esr);
|
|
writew(0x7FF, ®->gis);
|
|
bfin_can_err(dev, isrc, status);
|
|
} else {
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int bfin_can_open(struct net_device *dev)
|
|
{
|
|
struct bfin_can_priv *priv = netdev_priv(dev);
|
|
int err;
|
|
|
|
/* set chip into reset mode */
|
|
bfin_can_set_reset_mode(dev);
|
|
|
|
/* common open */
|
|
err = open_candev(dev);
|
|
if (err)
|
|
goto exit_open;
|
|
|
|
/* register interrupt handler */
|
|
err = request_irq(priv->rx_irq, &bfin_can_interrupt, 0,
|
|
"bfin-can-rx", dev);
|
|
if (err)
|
|
goto exit_rx_irq;
|
|
err = request_irq(priv->tx_irq, &bfin_can_interrupt, 0,
|
|
"bfin-can-tx", dev);
|
|
if (err)
|
|
goto exit_tx_irq;
|
|
err = request_irq(priv->err_irq, &bfin_can_interrupt, 0,
|
|
"bfin-can-err", dev);
|
|
if (err)
|
|
goto exit_err_irq;
|
|
|
|
bfin_can_start(dev);
|
|
|
|
netif_start_queue(dev);
|
|
|
|
return 0;
|
|
|
|
exit_err_irq:
|
|
free_irq(priv->tx_irq, dev);
|
|
exit_tx_irq:
|
|
free_irq(priv->rx_irq, dev);
|
|
exit_rx_irq:
|
|
close_candev(dev);
|
|
exit_open:
|
|
return err;
|
|
}
|
|
|
|
static int bfin_can_close(struct net_device *dev)
|
|
{
|
|
struct bfin_can_priv *priv = netdev_priv(dev);
|
|
|
|
netif_stop_queue(dev);
|
|
bfin_can_set_reset_mode(dev);
|
|
|
|
close_candev(dev);
|
|
|
|
free_irq(priv->rx_irq, dev);
|
|
free_irq(priv->tx_irq, dev);
|
|
free_irq(priv->err_irq, dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct net_device *alloc_bfin_candev(void)
|
|
{
|
|
struct net_device *dev;
|
|
struct bfin_can_priv *priv;
|
|
|
|
dev = alloc_candev(sizeof(*priv), TX_ECHO_SKB_MAX);
|
|
if (!dev)
|
|
return NULL;
|
|
|
|
priv = netdev_priv(dev);
|
|
|
|
priv->dev = dev;
|
|
priv->can.bittiming_const = &bfin_can_bittiming_const;
|
|
priv->can.do_set_bittiming = bfin_can_set_bittiming;
|
|
priv->can.do_set_mode = bfin_can_set_mode;
|
|
priv->can.do_get_berr_counter = bfin_can_get_berr_counter;
|
|
priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
|
|
|
|
return dev;
|
|
}
|
|
|
|
static const struct net_device_ops bfin_can_netdev_ops = {
|
|
.ndo_open = bfin_can_open,
|
|
.ndo_stop = bfin_can_close,
|
|
.ndo_start_xmit = bfin_can_start_xmit,
|
|
.ndo_change_mtu = can_change_mtu,
|
|
};
|
|
|
|
static int bfin_can_probe(struct platform_device *pdev)
|
|
{
|
|
int err;
|
|
struct net_device *dev;
|
|
struct bfin_can_priv *priv;
|
|
struct resource *res_mem, *rx_irq, *tx_irq, *err_irq;
|
|
unsigned short *pdata;
|
|
|
|
pdata = dev_get_platdata(&pdev->dev);
|
|
if (!pdata) {
|
|
dev_err(&pdev->dev, "No platform data provided!\n");
|
|
err = -EINVAL;
|
|
goto exit;
|
|
}
|
|
|
|
res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
rx_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
tx_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
|
|
err_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
|
|
if (!res_mem || !rx_irq || !tx_irq || !err_irq) {
|
|
err = -EINVAL;
|
|
goto exit;
|
|
}
|
|
|
|
/* request peripheral pins */
|
|
err = peripheral_request_list(pdata, dev_name(&pdev->dev));
|
|
if (err)
|
|
goto exit;
|
|
|
|
dev = alloc_bfin_candev();
|
|
if (!dev) {
|
|
err = -ENOMEM;
|
|
goto exit_peri_pin_free;
|
|
}
|
|
|
|
priv = netdev_priv(dev);
|
|
|
|
priv->membase = devm_ioremap_resource(&pdev->dev, res_mem);
|
|
if (IS_ERR(priv->membase)) {
|
|
err = PTR_ERR(priv->membase);
|
|
goto exit_peri_pin_free;
|
|
}
|
|
|
|
priv->rx_irq = rx_irq->start;
|
|
priv->tx_irq = tx_irq->start;
|
|
priv->err_irq = err_irq->start;
|
|
priv->pin_list = pdata;
|
|
priv->can.clock.freq = get_sclk();
|
|
|
|
platform_set_drvdata(pdev, dev);
|
|
SET_NETDEV_DEV(dev, &pdev->dev);
|
|
|
|
dev->flags |= IFF_ECHO; /* we support local echo */
|
|
dev->netdev_ops = &bfin_can_netdev_ops;
|
|
|
|
bfin_can_set_reset_mode(dev);
|
|
|
|
err = register_candev(dev);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "registering failed (err=%d)\n", err);
|
|
goto exit_candev_free;
|
|
}
|
|
|
|
dev_info(&pdev->dev,
|
|
"%s device registered"
|
|
"(®_base=%p, rx_irq=%d, tx_irq=%d, err_irq=%d, sclk=%d)\n",
|
|
DRV_NAME, priv->membase, priv->rx_irq,
|
|
priv->tx_irq, priv->err_irq, priv->can.clock.freq);
|
|
return 0;
|
|
|
|
exit_candev_free:
|
|
free_candev(dev);
|
|
exit_peri_pin_free:
|
|
peripheral_free_list(pdata);
|
|
exit:
|
|
return err;
|
|
}
|
|
|
|
static int bfin_can_remove(struct platform_device *pdev)
|
|
{
|
|
struct net_device *dev = platform_get_drvdata(pdev);
|
|
struct bfin_can_priv *priv = netdev_priv(dev);
|
|
|
|
bfin_can_set_reset_mode(dev);
|
|
|
|
unregister_candev(dev);
|
|
|
|
peripheral_free_list(priv->pin_list);
|
|
|
|
free_candev(dev);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int bfin_can_suspend(struct platform_device *pdev, pm_message_t mesg)
|
|
{
|
|
struct net_device *dev = platform_get_drvdata(pdev);
|
|
struct bfin_can_priv *priv = netdev_priv(dev);
|
|
struct bfin_can_regs __iomem *reg = priv->membase;
|
|
int timeout = BFIN_CAN_TIMEOUT;
|
|
|
|
if (netif_running(dev)) {
|
|
/* enter sleep mode */
|
|
writew(readw(®->control) | SMR, ®->control);
|
|
while (!(readw(®->intr) & SMACK)) {
|
|
udelay(10);
|
|
if (--timeout == 0) {
|
|
netdev_err(dev, "fail to enter sleep mode\n");
|
|
BUG();
|
|
}
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bfin_can_resume(struct platform_device *pdev)
|
|
{
|
|
struct net_device *dev = platform_get_drvdata(pdev);
|
|
struct bfin_can_priv *priv = netdev_priv(dev);
|
|
struct bfin_can_regs __iomem *reg = priv->membase;
|
|
|
|
if (netif_running(dev)) {
|
|
/* leave sleep mode */
|
|
writew(0, ®->intr);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
#define bfin_can_suspend NULL
|
|
#define bfin_can_resume NULL
|
|
#endif /* CONFIG_PM */
|
|
|
|
static struct platform_driver bfin_can_driver = {
|
|
.probe = bfin_can_probe,
|
|
.remove = bfin_can_remove,
|
|
.suspend = bfin_can_suspend,
|
|
.resume = bfin_can_resume,
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(bfin_can_driver);
|
|
|
|
MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("Blackfin on-chip CAN netdevice driver");
|
|
MODULE_ALIAS("platform:" DRV_NAME);
|