5e95329b70
This patch adds support for registering DSA switches using Device Tree bindings. Note that we support programming the switch routing table even though no in-tree user seems to require it. I tested this on Armada 370 with a Marvell 88E6172 (not supported by mainline yet). Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: David S. Miller <davem@davemloft.net>
92 lines
2.4 KiB
Plaintext
92 lines
2.4 KiB
Plaintext
Marvell Distributed Switch Architecture Device Tree Bindings
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------------------------------------------------------------
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Required properties:
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- compatible : Should be "marvell,dsa"
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- #address-cells : Must be 2, first cell is the address on the MDIO bus
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and second cell is the address in the switch tree.
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Second cell is used only when cascading/chaining.
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- #size-cells : Must be 0
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- dsa,ethernet : Should be a phandle to a valid Ethernet device node
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- dsa,mii-bus : Should be a phandle to a valid MDIO bus device node
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Optionnal properties:
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- interrupts : property with a value describing the switch
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interrupt number (not supported by the driver)
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A DSA node can contain multiple switch chips which are therefore child nodes of
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the parent DSA node. The maximum number of allowed child nodes is 4
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(DSA_MAX_SWITCHES).
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Each of these switch child nodes should have the following required properties:
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- reg : Describes the switch address on the MII bus
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- #address-cells : Must be 1
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- #size-cells : Must be 0
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A switch may have multiple "port" children nodes
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Each port children node must have the following mandatory properties:
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- reg : Describes the port address in the switch
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- label : Describes the label associated with this port, special
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labels are "cpu" to indicate a CPU port and "dsa" to
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indicate an uplink/downlink port.
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Note that a port labelled "dsa" will imply checking for the uplink phandle
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described below.
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Optionnal property:
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- link : Should be a phandle to another switch's DSA port.
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This property is only used when switches are being
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chained/cascaded together.
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Example:
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dsa@0 {
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compatible = "marvell,dsa";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <10>;
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dsa,ethernet = <ðernet0>;
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dsa,mii-bus = <&mii_bus0>;
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switch@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <16 0>; /* MDIO address 16, switch 0 in tree */
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port@0 {
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reg = <0>;
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label = "lan1";
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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};
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port@5 {
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reg = <5>;
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label = "cpu";
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};
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switch0uplink: port@6 {
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reg = <6>;
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label = "dsa";
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link = <&switch1uplink>;
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};
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};
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switch@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <17 1>; /* MDIO address 17, switch 1 in tree */
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switch1uplink: port@0 {
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reg = <0>;
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label = "dsa";
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link = <&switch0uplink>;
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};
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};
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};
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