linux/Documentation/devicetree/bindings/arm/omap
Afzal Mohammed 27b7d5f3cc bus: omap_l3_noc: Add AM4372 interconnect error data
Add AM4372 information to handle L3 error.

AM4372 has two clk domains 100f and 200s. Provide flagmux and data
associated with it.

NOTE: Timeout doesn't have STDERRLOG_MAIN register. And per hardware
team, L3 timeout error cannot be cleared the normal way (by setting
bit 31 in STDERRLOG_MAIN), instead it may be required to do system
reset. L3 error handler can't help in such scenarios.

Hence indicate timeout target offset as L3_TARGET_NOT_SUPPORTED as
done for undocumented bits.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
2014-05-05 14:34:37 -05:00
..
counter.txt ARM: dts: OMAP: Add counter-32k nodes 2012-10-29 16:56:33 +01:00
dsp.txt arm/dts: OMAP3+: Add mpu, dsp and iva nodes 2011-10-04 22:29:40 +02:00
intc.txt ARM: OMAP2/3: intc: Add DT support for TI interrupt controller 2012-02-27 10:33:18 +01:00
iva.txt arm/dts: OMAP3+: Add mpu, dsp and iva nodes 2011-10-04 22:29:40 +02:00
l3-noc.txt bus: omap_l3_noc: Add AM4372 interconnect error data 2014-05-05 14:34:37 -05:00
mpu.txt ARM: dts: doc: Document missing binding for omap5-mpu 2013-12-02 23:35:23 -06:00
omap.txt Documentation: dt: OMAP: Update Overo/Tobi 2014-02-14 08:37:53 -08:00
timer.txt ARM: dts: OMAP2+: Update DMTIMER compatibility property 2013-04-09 00:21:31 +02:00