forked from Minki/linux
26b7a78c55
This converts the lazy dcache handling to the model described in Documentation/cachetlb.txt and drops the ptep_get_and_clear() hacks used for the aliasing dcaches on SH-4 and SH7705 in 32kB mode. As a bonus, this slightly cuts down on the cache flushing frequency. With that and the PTEA handling out of the way, the update_mmu_cache() implementations can be consolidated, and we no longer have to worry about which configuration the cache is in for the SH7705 case. And finally, explicitly disable the lazy writeback on SMP (SH-4A). Signed-off-by: Paul Mundt <lethal@linux-sh.org>
38 lines
1.2 KiB
C
38 lines
1.2 KiB
C
#ifndef __ASM_SH_CACHEFLUSH_H
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#define __ASM_SH_CACHEFLUSH_H
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#ifdef __KERNEL__
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#include <linux/mm.h>
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#include <asm/cpu/cacheflush.h>
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/* Flush (write-back only) a region (smaller than a page) */
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extern void __flush_wback_region(void *start, int size);
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/* Flush (write-back & invalidate) a region (smaller than a page) */
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extern void __flush_purge_region(void *start, int size);
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/* Flush (invalidate only) a region (smaller than a page) */
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extern void __flush_invalidate_region(void *start, int size);
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#define flush_cache_vmap(start, end) flush_cache_all()
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#define flush_cache_vunmap(start, end) flush_cache_all()
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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flush_cache_page(vma, vaddr, page_to_pfn(page));\
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memcpy(dst, src, len); \
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flush_icache_user_range(vma, page, vaddr, len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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flush_cache_page(vma, vaddr, page_to_pfn(page));\
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memcpy(dst, src, len); \
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} while (0)
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#define HAVE_ARCH_UNMAPPED_AREA
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/* Page flag for lazy dcache write-back for the aliasing UP caches */
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#define PG_dcache_dirty PG_arch_1
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#endif /* __KERNEL__ */
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#endif /* __ASM_SH_CACHEFLUSH_H */
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