forked from Minki/linux
2d8e898e09
APU fb offset is set by sbios, which is different with DGPU. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
431 lines
13 KiB
C
431 lines
13 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "gfxhub_v1_0.h"
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#include "vega10/soc15ip.h"
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#include "vega10/GC/gc_9_0_offset.h"
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#include "vega10/GC/gc_9_0_sh_mask.h"
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#include "vega10/GC/gc_9_0_default.h"
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#include "vega10/vega10_enum.h"
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#include "soc15_common.h"
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u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
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{
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return (u64)RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_OFFSET)) << 24;
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}
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int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
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{
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u32 tmp;
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u64 value;
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u32 i;
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/* Program MC. */
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/* Update configuration */
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WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
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adev->mc.vram_start >> 18);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),
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adev->mc.vram_end >> 18);
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value = adev->vram_scratch.gpu_addr - adev->mc.vram_start
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+ adev->vm_manager.vram_base_offset;
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),
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(u32)(value >> 12));
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),
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(u32)(value >> 44));
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if (amdgpu_sriov_vf(adev)) {
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/* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so
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vbios post doesn't program them, for SRIOV driver need to program them */
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WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE),
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adev->mc.vram_start >> 24);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP),
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adev->mc.vram_end >> 24);
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}
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/* Disable AGP. */
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WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BASE), 0);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_TOP), 0);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BOT), 0xFFFFFFFF);
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/* GART Enable. */
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/* Setup TLB control */
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tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
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tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
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tmp = REG_SET_FIELD(tmp,
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MC_VM_MX_L1_TLB_CNTL,
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SYSTEM_ACCESS_MODE,
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3);
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tmp = REG_SET_FIELD(tmp,
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MC_VM_MX_L1_TLB_CNTL,
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ENABLE_ADVANCED_DRIVER_MODEL,
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1);
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tmp = REG_SET_FIELD(tmp,
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MC_VM_MX_L1_TLB_CNTL,
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SYSTEM_APERTURE_UNMAPPED_ACCESS,
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0);
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tmp = REG_SET_FIELD(tmp,
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MC_VM_MX_L1_TLB_CNTL,
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ECO_BITS,
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0);
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tmp = REG_SET_FIELD(tmp,
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MC_VM_MX_L1_TLB_CNTL,
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MTYPE,
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MTYPE_UC);/* XXX for emulation. */
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tmp = REG_SET_FIELD(tmp,
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MC_VM_MX_L1_TLB_CNTL,
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ATC_EN,
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1);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
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/* Setup L2 cache */
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tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));
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tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
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tmp = REG_SET_FIELD(tmp,
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VM_L2_CNTL,
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ENABLE_L2_FRAGMENT_PROCESSING,
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0);
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tmp = REG_SET_FIELD(tmp,
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VM_L2_CNTL,
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L2_PDE0_CACHE_TAG_GENERATION_MODE,
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0);/* XXX for emulation, Refer to closed source code.*/
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tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
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tmp = REG_SET_FIELD(tmp,
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VM_L2_CNTL,
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CONTEXT1_IDENTITY_ACCESS_MODE,
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1);
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tmp = REG_SET_FIELD(tmp,
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VM_L2_CNTL,
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IDENTITY_MODE_FRAGMENT_SIZE,
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0);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);
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tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2));
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tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
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tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2), tmp);
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tmp = mmVM_L2_CNTL3_DEFAULT;
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WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), tmp);
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tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4));
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tmp = REG_SET_FIELD(tmp,
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VM_L2_CNTL4,
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VMC_TAP_PDE_REQUEST_PHYSICAL,
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0);
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tmp = REG_SET_FIELD(tmp,
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VM_L2_CNTL4,
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VMC_TAP_PTE_REQUEST_PHYSICAL,
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0);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);
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/* setup context0 */
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
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(u32)(adev->mc.gtt_start >> 12));
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
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(u32)(adev->mc.gtt_start >> 44));
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
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(u32)(adev->mc.gtt_end >> 12));
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
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(u32)(adev->mc.gtt_end >> 44));
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BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
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value = adev->gart.table_addr - adev->mc.vram_start
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+ adev->vm_manager.vram_base_offset;
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value &= 0x0000FFFFFFFFF000ULL;
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value |= 0x1; /*valid bit*/
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
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(u32)value);
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
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(u32)(value >> 32));
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
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(u32)(adev->dummy_page.addr >> 12));
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),
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(u32)((u64)adev->dummy_page.addr >> 44));
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tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2));
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tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
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ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY,
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1);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp);
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tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL));
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp);
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/* Disable identity aperture.*/
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF);
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
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for (i = 0; i <= 14; i++) {
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tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
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adev->vm_manager.num_level);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
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RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
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DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
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PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
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VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
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READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
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WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
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EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
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PAGE_TABLE_BLOCK_SIZE,
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adev->vm_manager.block_size - 9);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i, tmp);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32) + i*2, 0);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32) + i*2, 0);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32) + i*2,
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lower_32_bits(adev->vm_manager.max_pfn - 1));
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WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2,
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upper_32_bits(adev->vm_manager.max_pfn - 1));
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}
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return 0;
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}
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void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
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{
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u32 tmp;
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u32 i;
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/* Disable all tables */
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for (i = 0; i < 16; i++)
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WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL) + i, 0);
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/* Setup TLB control */
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tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
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tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
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tmp = REG_SET_FIELD(tmp,
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MC_VM_MX_L1_TLB_CNTL,
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ENABLE_ADVANCED_DRIVER_MODEL,
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0);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
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/* Setup L2 cache */
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tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));
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tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), 0);
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}
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/**
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* gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling
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*
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* @adev: amdgpu_device pointer
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* @value: true redirects VM faults to the default page
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*/
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void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
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bool value)
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{
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u32 tmp;
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tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL));
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tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
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RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
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PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
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PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
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PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp,
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VM_L2_PROTECTION_FAULT_CNTL,
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TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
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value);
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tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
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NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
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DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
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VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
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READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
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WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
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EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
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}
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static int gfxhub_v1_0_early_init(void *handle)
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{
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return 0;
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}
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static int gfxhub_v1_0_late_init(void *handle)
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{
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return 0;
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}
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static int gfxhub_v1_0_sw_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];
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hub->ctx0_ptb_addr_lo32 =
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SOC15_REG_OFFSET(GC, 0,
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mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
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hub->ctx0_ptb_addr_hi32 =
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SOC15_REG_OFFSET(GC, 0,
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mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
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hub->vm_inv_eng0_req =
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SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
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hub->vm_inv_eng0_ack =
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SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);
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hub->vm_context0_cntl =
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SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
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hub->vm_l2_pro_fault_status =
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SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
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hub->vm_l2_pro_fault_cntl =
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SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
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return 0;
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}
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static int gfxhub_v1_0_sw_fini(void *handle)
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{
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return 0;
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}
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static int gfxhub_v1_0_hw_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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unsigned i;
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for (i = 0 ; i < 18; ++i) {
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) +
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2 * i, 0xffffffff);
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) +
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2 * i, 0x1f);
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}
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return 0;
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}
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static int gfxhub_v1_0_hw_fini(void *handle)
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{
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return 0;
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}
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static int gfxhub_v1_0_suspend(void *handle)
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{
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return 0;
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}
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static int gfxhub_v1_0_resume(void *handle)
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{
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return 0;
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}
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static bool gfxhub_v1_0_is_idle(void *handle)
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{
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return true;
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}
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static int gfxhub_v1_0_wait_for_idle(void *handle)
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{
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return 0;
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}
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static int gfxhub_v1_0_soft_reset(void *handle)
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{
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return 0;
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}
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static int gfxhub_v1_0_set_clockgating_state(void *handle,
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enum amd_clockgating_state state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int gfxhub_v1_0_set_powergating_state(void *handle,
|
|
enum amd_powergating_state state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
const struct amd_ip_funcs gfxhub_v1_0_ip_funcs = {
|
|
.name = "gfxhub_v1_0",
|
|
.early_init = gfxhub_v1_0_early_init,
|
|
.late_init = gfxhub_v1_0_late_init,
|
|
.sw_init = gfxhub_v1_0_sw_init,
|
|
.sw_fini = gfxhub_v1_0_sw_fini,
|
|
.hw_init = gfxhub_v1_0_hw_init,
|
|
.hw_fini = gfxhub_v1_0_hw_fini,
|
|
.suspend = gfxhub_v1_0_suspend,
|
|
.resume = gfxhub_v1_0_resume,
|
|
.is_idle = gfxhub_v1_0_is_idle,
|
|
.wait_for_idle = gfxhub_v1_0_wait_for_idle,
|
|
.soft_reset = gfxhub_v1_0_soft_reset,
|
|
.set_clockgating_state = gfxhub_v1_0_set_clockgating_state,
|
|
.set_powergating_state = gfxhub_v1_0_set_powergating_state,
|
|
};
|
|
|
|
const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block =
|
|
{
|
|
.type = AMD_IP_BLOCK_TYPE_GFXHUB,
|
|
.major = 1,
|
|
.minor = 0,
|
|
.rev = 0,
|
|
.funcs = &gfxhub_v1_0_ip_funcs,
|
|
};
|