forked from Minki/linux
263475d4e0
RBC is to control whether some ANATOP sub modules can enter lpm mode when SOC is into STOP mode, if RBC is enabled and PMIC_VSTBY_REQ is set, ANATOP will have below behaviors: 1. Digital LDOs(CORE, SOC and PU) are bypassed; 2. Analog LDOs(1P1, 2P5, 3P0) are disabled; As the 2P5 is necessary for DRAM IO pre-drive in STOP mode, so we need to enable weak 2P5 in STOP mode when 2P5 LDO is disabled. For RBC settings, there are some rules as below due to hardware design: 1. All interrupts must be masked during operating RBC registers; 2. At least 2 CKIL(32K) cycles is needed after the RBC setting is changed. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
163 lines
5.2 KiB
C
163 lines
5.2 KiB
C
/*
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* Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_MXC_COMMON_H__
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#define __ASM_ARCH_MXC_COMMON_H__
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struct platform_device;
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struct clk;
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enum mxc_cpu_pwr_mode;
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extern void mx1_map_io(void);
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extern void mx21_map_io(void);
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extern void mx25_map_io(void);
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extern void mx27_map_io(void);
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extern void mx31_map_io(void);
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extern void mx35_map_io(void);
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extern void mx51_map_io(void);
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extern void mx53_map_io(void);
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extern void imx1_init_early(void);
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extern void imx21_init_early(void);
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extern void imx25_init_early(void);
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extern void imx27_init_early(void);
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extern void imx31_init_early(void);
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extern void imx35_init_early(void);
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extern void imx51_init_early(void);
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extern void imx53_init_early(void);
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extern void mxc_init_irq(void __iomem *);
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extern void tzic_init_irq(void __iomem *);
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extern void mx1_init_irq(void);
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extern void mx21_init_irq(void);
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extern void mx25_init_irq(void);
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extern void mx27_init_irq(void);
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extern void mx31_init_irq(void);
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extern void mx35_init_irq(void);
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extern void mx51_init_irq(void);
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extern void mx53_init_irq(void);
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extern void imx1_soc_init(void);
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extern void imx21_soc_init(void);
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extern void imx25_soc_init(void);
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extern void imx27_soc_init(void);
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extern void imx31_soc_init(void);
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extern void imx35_soc_init(void);
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extern void imx51_soc_init(void);
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extern void imx51_init_late(void);
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extern void imx53_init_late(void);
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extern void epit_timer_init(void __iomem *base, int irq);
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extern void mxc_timer_init(void __iomem *, int);
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extern int mx1_clocks_init(unsigned long fref);
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extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
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extern int mx25_clocks_init(void);
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extern int mx27_clocks_init(unsigned long fref);
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extern int mx31_clocks_init(unsigned long fref);
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extern int mx35_clocks_init(void);
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extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
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unsigned long ckih1, unsigned long ckih2);
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extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
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unsigned long ckih1, unsigned long ckih2);
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extern int mx25_clocks_init_dt(void);
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extern int mx27_clocks_init_dt(void);
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extern int mx31_clocks_init_dt(void);
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extern int mx51_clocks_init_dt(void);
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extern int mx53_clocks_init_dt(void);
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extern int mx6q_clocks_init(void);
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extern struct platform_device *mxc_register_gpio(char *name, int id,
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resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
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extern void mxc_set_cpu_type(unsigned int type);
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extern void mxc_restart(char, const char *);
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extern void mxc_arch_reset_init(void __iomem *);
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extern int mx53_revision(void);
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extern int mx53_display_revision(void);
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extern void imx_set_aips(void __iomem *);
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extern int mxc_device_init(void);
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enum mxc_cpu_pwr_mode {
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WAIT_CLOCKED, /* wfi only */
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WAIT_UNCLOCKED, /* WAIT */
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WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
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STOP_POWER_ON, /* just STOP */
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STOP_POWER_OFF, /* STOP + SRPG */
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};
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enum mx3_cpu_pwr_mode {
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MX3_RUN,
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MX3_WAIT,
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MX3_DOZE,
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MX3_SLEEP,
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};
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extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
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extern void imx_print_silicon_rev(const char *cpu, int srev);
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void avic_handle_irq(struct pt_regs *);
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void tzic_handle_irq(struct pt_regs *);
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#define imx1_handle_irq avic_handle_irq
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#define imx21_handle_irq avic_handle_irq
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#define imx25_handle_irq avic_handle_irq
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#define imx27_handle_irq avic_handle_irq
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#define imx31_handle_irq avic_handle_irq
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#define imx35_handle_irq avic_handle_irq
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#define imx51_handle_irq tzic_handle_irq
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#define imx53_handle_irq tzic_handle_irq
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extern void imx_enable_cpu(int cpu, bool enable);
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extern void imx_set_cpu_jump(int cpu, void *jump_addr);
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extern u32 imx_get_cpu_arg(int cpu);
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extern void imx_set_cpu_arg(int cpu, u32 arg);
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extern void v7_cpu_resume(void);
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#ifdef CONFIG_SMP
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extern void v7_secondary_startup(void);
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extern void imx_scu_map_io(void);
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extern void imx_smp_prepare(void);
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extern void imx_scu_standby_enable(void);
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#else
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static inline void imx_scu_map_io(void) {}
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static inline void imx_smp_prepare(void) {}
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static inline void imx_scu_standby_enable(void) {}
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#endif
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extern void imx_src_init(void);
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extern void imx_src_prepare_restart(void);
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extern void imx_gpc_init(void);
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extern void imx_gpc_pre_suspend(void);
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extern void imx_gpc_post_resume(void);
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extern void imx_gpc_mask_all(void);
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extern void imx_gpc_restore_all(void);
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extern void imx_anatop_init(void);
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extern void imx_anatop_pre_suspend(void);
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extern void imx_anatop_post_resume(void);
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extern void imx_anatop_usb_chrg_detect_disable(void);
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extern u32 imx_anatop_get_digprog(void);
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extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
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extern void imx6q_set_chicken_bit(void);
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extern void imx_cpu_die(unsigned int cpu);
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extern int imx_cpu_kill(unsigned int cpu);
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#ifdef CONFIG_PM
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extern void imx6q_pm_init(void);
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extern void imx51_pm_init(void);
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extern void imx53_pm_init(void);
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#else
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static inline void imx6q_pm_init(void) {}
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static inline void imx51_pm_init(void) {}
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static inline void imx53_pm_init(void) {}
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#endif
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#ifdef CONFIG_NEON
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extern int mx51_neon_fixup(void);
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#else
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static inline int mx51_neon_fixup(void) { return 0; }
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#endif
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extern struct smp_operations imx_smp_ops;
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#endif
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