forked from Minki/linux
25fdd5933e
SDM845 SoC includes the Mobile Display Sub System (MDSS) which is a
top level wrapper consisting of Display Processing Unit (DPU) and
display peripheral modules such as Display Serial Interface (DSI)
and DisplayPort (DP).
MDSS functions essentially as a back-end composition engine. It blends
video and graphic images stored in the frame buffers and scans out the
composed image to a display sink (over DSI/DP).
The following diagram represents hardware blocks for a simple pipeline
(two planes are present on a given crtc which is connected to a DSI
connector):
MDSS
+---------------------------------+
| +-----------------------------+ |
| | DPU | |
| | +--------+ +--------+ | |
| | | SSPP | | SSPP | | |
| | +----+---+ +----+---+ | |
| | | | | |
| | +----v-----------v---+ | |
| | | Layer Mixer (LM) | | |
| | +--------------------+ | |
| | +--------------------+ | |
| | | PingPong (PP) | | |
| | +--------------------+ | |
| | +--------------------+ | |
| | | INTERFACE (VIDEO) | | |
| | +---+----------------+ | |
| +------|----------------------+ |
| | |
| +------|---------------------+ |
| | | DISPLAY PERIPHERALS | |
| | +---v-+ +-----+ | |
| | | DSI | | DP | | |
| | +-----+ +-----+ | |
| +----------------------------+ |
+---------------------------------+
The number of DPU sub-blocks (i.e. SSPPs, LMs, PP blocks and INTFs)
depends on SoC capabilities.
Overview of DPU sub-blocks:
---------------------------
* Source Surface Processor (SSPP):
Refers to any of hardware pipes like ViG, DMA etc. Only ViG pipes are
capable of performing format conversion, scaling and quality improvement
for source surfaces.
* Layer Mixer (LM):
Blend source surfaces together (in requested zorder)
* PingPong (PP):
This block controls frame done interrupt output, EOL and EOF generation,
overflow/underflow control.
* Display interface (INTF):
Timing generator and interface connecting the display peripherals.
DRM components mapping to DPU architecture:
------------------------------------------
PLANEs maps to SSPPs
CRTC maps to LMs
Encoder maps to PPs, INTFs
Data flow setup:
---------------
MDSS hardware can support various data flows (e.g.):
- Dual pipe: Output from two LMs combined to single display.
- Split display: Output from two LMs connected to two separate
interfaces.
The hardware capabilities determine the number of concurrent data paths
possible. Any control path (i.e. pipeline w/i DPU) can be routed to any
of the hardware data paths. A given control path can be triggered,
flushed and controlled independently.
Changes in v3:
- Move msm_media_info.h from uapi to dpu/ subdir
- Remove preclose callback dpu (it's handled in core)
- Fix kbuild warnings with parent_ops
- Remove unused functions from dpu_core_irq
- Rename mdss_phys to mdss
- Rename mdp_phys address space to mdp
- Drop _phys from vbif and regdma binding names
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org>
Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
[robclark minor rebase]
Signed-off-by: Rob Clark <robdclark@gmail.com>
127 lines
3.3 KiB
Makefile
127 lines
3.3 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
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ccflags-y := -Idrivers/gpu/drm/msm
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ccflags-y += -Idrivers/gpu/drm/msm/disp/dpu1
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ccflags-$(CONFIG_DRM_MSM_DSI) += -Idrivers/gpu/drm/msm/dsi
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msm-y := \
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adreno/adreno_device.o \
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adreno/adreno_gpu.o \
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adreno/a3xx_gpu.o \
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adreno/a4xx_gpu.o \
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adreno/a5xx_gpu.o \
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adreno/a5xx_power.o \
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adreno/a5xx_preempt.o \
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hdmi/hdmi.o \
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hdmi/hdmi_audio.o \
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hdmi/hdmi_bridge.o \
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hdmi/hdmi_connector.o \
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hdmi/hdmi_i2c.o \
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hdmi/hdmi_phy.o \
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hdmi/hdmi_phy_8960.o \
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hdmi/hdmi_phy_8x60.o \
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hdmi/hdmi_phy_8x74.o \
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edp/edp.o \
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edp/edp_aux.o \
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edp/edp_bridge.o \
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edp/edp_connector.o \
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edp/edp_ctrl.o \
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edp/edp_phy.o \
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disp/mdp_format.o \
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disp/mdp_kms.o \
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disp/mdp4/mdp4_crtc.o \
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disp/mdp4/mdp4_dtv_encoder.o \
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disp/mdp4/mdp4_lcdc_encoder.o \
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disp/mdp4/mdp4_lvds_connector.o \
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disp/mdp4/mdp4_irq.o \
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disp/mdp4/mdp4_kms.o \
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disp/mdp4/mdp4_plane.o \
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disp/mdp5/mdp5_cfg.o \
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disp/mdp5/mdp5_ctl.o \
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disp/mdp5/mdp5_crtc.o \
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disp/mdp5/mdp5_encoder.o \
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disp/mdp5/mdp5_irq.o \
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disp/mdp5/mdp5_mdss.o \
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disp/mdp5/mdp5_kms.o \
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disp/mdp5/mdp5_pipe.o \
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disp/mdp5/mdp5_mixer.o \
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disp/mdp5/mdp5_plane.o \
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disp/mdp5/mdp5_smp.o \
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disp/dpu1/dpu_core_irq.o \
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disp/dpu1/dpu_core_perf.o \
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disp/dpu1/dpu_crtc.o \
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disp/dpu1/dpu_encoder.o \
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disp/dpu1/dpu_encoder_phys_cmd.o \
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disp/dpu1/dpu_encoder_phys_vid.o \
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disp/dpu1/dpu_formats.o \
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disp/dpu1/dpu_hw_blk.o \
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disp/dpu1/dpu_hw_catalog.o \
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disp/dpu1/dpu_hw_cdm.o \
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disp/dpu1/dpu_hw_ctl.o \
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disp/dpu1/dpu_hw_interrupts.o \
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disp/dpu1/dpu_hw_intf.o \
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disp/dpu1/dpu_hw_lm.o \
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disp/dpu1/dpu_hw_pingpong.o \
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disp/dpu1/dpu_hw_sspp.o \
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disp/dpu1/dpu_hw_top.o \
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disp/dpu1/dpu_hw_util.o \
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disp/dpu1/dpu_hw_vbif.o \
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disp/dpu1/dpu_io_util.o \
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disp/dpu1/dpu_irq.o \
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disp/dpu1/dpu_kms.o \
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disp/dpu1/dpu_kms_utils.o \
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disp/dpu1/dpu_mdss.o \
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disp/dpu1/dpu_plane.o \
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disp/dpu1/dpu_power_handle.o \
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disp/dpu1/dpu_rm.o \
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disp/dpu1/dpu_vbif.o \
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msm_atomic.o \
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msm_debugfs.o \
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msm_drv.o \
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msm_fb.o \
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msm_fence.o \
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msm_gem.o \
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msm_gem_prime.o \
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msm_gem_shrinker.o \
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msm_gem_submit.o \
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msm_gem_vma.o \
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msm_gpu.o \
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msm_iommu.o \
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msm_perf.o \
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msm_rd.o \
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msm_ringbuffer.o \
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msm_submitqueue.o
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msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \
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disp/dpu1/dpu_dbg.o
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msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
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msm-$(CONFIG_COMMON_CLK) += disp/mdp4/mdp4_lvds_pll.o
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msm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_pll_8960.o
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msm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_phy_8996.o
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msm-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o
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msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
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disp/mdp4/mdp4_dsi_encoder.o \
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dsi/dsi_cfg.o \
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dsi/dsi_host.o \
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dsi/dsi_manager.o \
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dsi/phy/dsi_phy.o \
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disp/mdp5/mdp5_cmd_encoder.o
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msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o
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msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o
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msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o
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msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o
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msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o
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ifeq ($(CONFIG_DRM_MSM_DSI_PLL),y)
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msm-y += dsi/pll/dsi_pll.o
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msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/pll/dsi_pll_28nm.o
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msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/pll/dsi_pll_28nm_8960.o
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msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/pll/dsi_pll_14nm.o
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msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/pll/dsi_pll_10nm.o
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endif
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obj-$(CONFIG_DRM_MSM) += msm.o
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