forked from Minki/linux
275 lines
6.3 KiB
C
275 lines
6.3 KiB
C
/*
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* arch/arm/mach-kirkwood/pcie.c
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*
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* PCIe functions for Marvell Kirkwood SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/mbus.h>
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#include <asm/irq.h>
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#include <asm/mach/pci.h>
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#include <plat/pcie.h>
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#include <mach/bridge-regs.h>
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#include "common.h"
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void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
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{
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*dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
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*rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
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}
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struct pcie_port {
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u8 root_bus_nr;
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void __iomem *base;
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spinlock_t conf_lock;
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int irq;
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struct resource res[2];
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};
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static int pcie_port_map[2];
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static int num_pcie_ports;
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static inline struct pcie_port *bus_to_port(struct pci_bus *bus)
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{
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struct pci_sys_data *sys = bus->sysdata;
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return sys->private_data;
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}
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static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
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{
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/*
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* Don't go out when trying to access --
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* 1. nonexisting device on local bus
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* 2. where there's no device connected (no link)
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*/
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if (bus == pp->root_bus_nr && dev == 0)
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return 1;
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if (!orion_pcie_link_up(pp->base))
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return 0;
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if (bus == pp->root_bus_nr && dev != 1)
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return 0;
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return 1;
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}
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/*
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* PCIe config cycles are done by programming the PCIE_CONF_ADDR register
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* and then reading the PCIE_CONF_DATA register. Need to make sure these
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* transactions are atomic.
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*/
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static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
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int size, u32 *val)
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{
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struct pcie_port *pp = bus_to_port(bus);
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unsigned long flags;
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int ret;
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if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
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*val = 0xffffffff;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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spin_lock_irqsave(&pp->conf_lock, flags);
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ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
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spin_unlock_irqrestore(&pp->conf_lock, flags);
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return ret;
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}
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static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
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int where, int size, u32 val)
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{
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struct pcie_port *pp = bus_to_port(bus);
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unsigned long flags;
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int ret;
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if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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spin_lock_irqsave(&pp->conf_lock, flags);
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ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
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spin_unlock_irqrestore(&pp->conf_lock, flags);
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return ret;
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}
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static struct pci_ops pcie_ops = {
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.read = pcie_rd_conf,
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.write = pcie_wr_conf,
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};
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static void __init pcie0_ioresources_init(struct pcie_port *pp)
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{
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pp->base = (void __iomem *)PCIE_VIRT_BASE;
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pp->irq = IRQ_KIRKWOOD_PCIE;
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/*
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* IORESOURCE_IO
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*/
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pp->res[0].name = "PCIe 0 I/O Space";
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pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
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pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
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pp->res[0].flags = IORESOURCE_IO;
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/*
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* IORESOURCE_MEM
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*/
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pp->res[1].name = "PCIe 0 MEM";
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pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
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pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
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pp->res[1].flags = IORESOURCE_MEM;
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}
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static void __init pcie1_ioresources_init(struct pcie_port *pp)
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{
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pp->base = (void __iomem *)PCIE1_VIRT_BASE;
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pp->irq = IRQ_KIRKWOOD_PCIE1;
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/*
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* IORESOURCE_IO
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*/
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pp->res[0].name = "PCIe 1 I/O Space";
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pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
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pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
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pp->res[0].flags = IORESOURCE_IO;
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/*
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* IORESOURCE_MEM
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*/
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pp->res[1].name = "PCIe 1 MEM";
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pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
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pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
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pp->res[1].flags = IORESOURCE_MEM;
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}
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static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
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{
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extern unsigned int kirkwood_clk_ctrl;
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struct pcie_port *pp;
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int index;
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if (nr >= num_pcie_ports)
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return 0;
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index = pcie_port_map[nr];
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printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
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pp = kzalloc(sizeof(*pp), GFP_KERNEL);
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if (!pp)
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panic("PCIe: failed to allocate pcie_port data");
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sys->private_data = pp;
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pp->root_bus_nr = sys->busnr;
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spin_lock_init(&pp->conf_lock);
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switch (index) {
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case 0:
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kirkwood_clk_ctrl |= CGC_PEX0;
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pcie0_ioresources_init(pp);
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break;
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case 1:
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kirkwood_clk_ctrl |= CGC_PEX1;
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pcie1_ioresources_init(pp);
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break;
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default:
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panic("PCIe setup: invalid controller %d", index);
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}
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if (request_resource(&ioport_resource, &pp->res[0]))
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panic("Request PCIe%d IO resource failed\n", index);
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if (request_resource(&iomem_resource, &pp->res[1]))
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panic("Request PCIe%d Memory resource failed\n", index);
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sys->resource[0] = &pp->res[0];
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sys->resource[1] = &pp->res[1];
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sys->resource[2] = NULL;
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sys->io_offset = 0;
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/*
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* Generic PCIe unit setup.
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*/
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orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
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orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
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return 1;
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}
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static void __devinit rc_pci_fixup(struct pci_dev *dev)
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{
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/*
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* Prevent enumeration of root complex.
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*/
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if (dev->bus->parent == NULL && dev->devfn == 0) {
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int i;
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for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
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dev->resource[i].start = 0;
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dev->resource[i].end = 0;
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dev->resource[i].flags = 0;
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}
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
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static struct pci_bus __init *
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kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
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{
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struct pci_bus *bus;
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if (nr < num_pcie_ports) {
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bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
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} else {
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bus = NULL;
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BUG();
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}
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return bus;
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}
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static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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struct pcie_port *pp = bus_to_port(dev->bus);
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return pp->irq;
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}
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static struct hw_pci kirkwood_pci __initdata = {
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.swizzle = pci_std_swizzle,
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.setup = kirkwood_pcie_setup,
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.scan = kirkwood_pcie_scan_bus,
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.map_irq = kirkwood_pcie_map_irq,
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};
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static void __init add_pcie_port(int index, unsigned long base)
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{
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printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
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if (orion_pcie_link_up((void __iomem *)base)) {
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printk(KERN_INFO "link up\n");
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pcie_port_map[num_pcie_ports++] = index;
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} else
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printk(KERN_INFO "link down, ignoring\n");
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}
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void __init kirkwood_pcie_init(unsigned int portmask)
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{
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if (portmask & KW_PCIE0)
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add_pcie_port(0, PCIE_VIRT_BASE);
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if (portmask & KW_PCIE1)
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add_pcie_port(1, PCIE1_VIRT_BASE);
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kirkwood_pci.nr_controllers = num_pcie_ports;
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pci_common_init(&kirkwood_pci);
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}
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