forked from Minki/linux
9b05a69e05
Fix up the arguments to arch_ptrace() to take account of the fact that @addr and @data are now unsigned long rather than long as of a preceding patch in this series. Signed-off-by: Namhyung Kim <namhyung@gmail.com> Cc: <linux-arch@vger.kernel.org> Acked-by: Roland McGrath <roland@redhat.com> Acked-by: David Howells <dhowells@redhat.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
338 lines
9.0 KiB
C
338 lines
9.0 KiB
C
/* ptrace.c */
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/* By Ross Biro 1/23/92 */
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/* edited by Linus Torvalds */
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/* mangled further by Bob Manson (manson@santafe.edu) */
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/* more mutilation by David Mosberger (davidm@azstarnet.com) */
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/errno.h>
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#include <linux/ptrace.h>
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#include <linux/user.h>
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#include <linux/security.h>
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#include <linux/signal.h>
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#include <asm/uaccess.h>
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#include <asm/pgtable.h>
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#include <asm/system.h>
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#include <asm/fpu.h>
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#include "proto.h"
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#define DEBUG DBG_MEM
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#undef DEBUG
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#ifdef DEBUG
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enum {
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DBG_MEM = (1<<0),
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DBG_BPT = (1<<1),
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DBG_MEM_ALL = (1<<2)
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};
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#define DBG(fac,args) {if ((fac) & DEBUG) printk args;}
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#else
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#define DBG(fac,args)
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#endif
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#define BREAKINST 0x00000080 /* call_pal bpt */
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/*
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* does not yet catch signals sent when the child dies.
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* in exit.c or in signal.c.
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*/
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/*
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* Processes always block with the following stack-layout:
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*
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* +================================+ <---- task + 2*PAGE_SIZE
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* | PALcode saved frame (ps, pc, | ^
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* | gp, a0, a1, a2) | |
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* +================================+ | struct pt_regs
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* | | |
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* | frame generated by SAVE_ALL | |
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* | | v
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* +================================+
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* | | ^
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* | frame saved by do_switch_stack | | struct switch_stack
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* | | v
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* +================================+
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*/
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/*
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* The following table maps a register index into the stack offset at
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* which the register is saved. Register indices are 0-31 for integer
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* regs, 32-63 for fp regs, and 64 for the pc. Notice that sp and
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* zero have no stack-slot and need to be treated specially (see
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* get_reg/put_reg below).
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*/
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enum {
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REG_R0 = 0, REG_F0 = 32, REG_FPCR = 63, REG_PC = 64
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};
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#define PT_REG(reg) \
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(PAGE_SIZE*2 - sizeof(struct pt_regs) + offsetof(struct pt_regs, reg))
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#define SW_REG(reg) \
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(PAGE_SIZE*2 - sizeof(struct pt_regs) - sizeof(struct switch_stack) \
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+ offsetof(struct switch_stack, reg))
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static int regoff[] = {
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PT_REG( r0), PT_REG( r1), PT_REG( r2), PT_REG( r3),
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PT_REG( r4), PT_REG( r5), PT_REG( r6), PT_REG( r7),
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PT_REG( r8), SW_REG( r9), SW_REG( r10), SW_REG( r11),
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SW_REG( r12), SW_REG( r13), SW_REG( r14), SW_REG( r15),
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PT_REG( r16), PT_REG( r17), PT_REG( r18), PT_REG( r19),
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PT_REG( r20), PT_REG( r21), PT_REG( r22), PT_REG( r23),
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PT_REG( r24), PT_REG( r25), PT_REG( r26), PT_REG( r27),
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PT_REG( r28), PT_REG( gp), -1, -1,
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SW_REG(fp[ 0]), SW_REG(fp[ 1]), SW_REG(fp[ 2]), SW_REG(fp[ 3]),
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SW_REG(fp[ 4]), SW_REG(fp[ 5]), SW_REG(fp[ 6]), SW_REG(fp[ 7]),
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SW_REG(fp[ 8]), SW_REG(fp[ 9]), SW_REG(fp[10]), SW_REG(fp[11]),
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SW_REG(fp[12]), SW_REG(fp[13]), SW_REG(fp[14]), SW_REG(fp[15]),
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SW_REG(fp[16]), SW_REG(fp[17]), SW_REG(fp[18]), SW_REG(fp[19]),
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SW_REG(fp[20]), SW_REG(fp[21]), SW_REG(fp[22]), SW_REG(fp[23]),
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SW_REG(fp[24]), SW_REG(fp[25]), SW_REG(fp[26]), SW_REG(fp[27]),
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SW_REG(fp[28]), SW_REG(fp[29]), SW_REG(fp[30]), SW_REG(fp[31]),
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PT_REG( pc)
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};
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static unsigned long zero;
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/*
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* Get address of register REGNO in task TASK.
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*/
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static unsigned long *
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get_reg_addr(struct task_struct * task, unsigned long regno)
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{
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unsigned long *addr;
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if (regno == 30) {
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addr = &task_thread_info(task)->pcb.usp;
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} else if (regno == 65) {
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addr = &task_thread_info(task)->pcb.unique;
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} else if (regno == 31 || regno > 65) {
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zero = 0;
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addr = &zero;
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} else {
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addr = task_stack_page(task) + regoff[regno];
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}
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return addr;
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}
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/*
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* Get contents of register REGNO in task TASK.
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*/
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static unsigned long
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get_reg(struct task_struct * task, unsigned long regno)
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{
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/* Special hack for fpcr -- combine hardware and software bits. */
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if (regno == 63) {
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unsigned long fpcr = *get_reg_addr(task, regno);
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unsigned long swcr
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= task_thread_info(task)->ieee_state & IEEE_SW_MASK;
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swcr = swcr_update_status(swcr, fpcr);
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return fpcr | swcr;
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}
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return *get_reg_addr(task, regno);
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}
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/*
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* Write contents of register REGNO in task TASK.
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*/
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static int
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put_reg(struct task_struct *task, unsigned long regno, unsigned long data)
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{
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if (regno == 63) {
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task_thread_info(task)->ieee_state
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= ((task_thread_info(task)->ieee_state & ~IEEE_SW_MASK)
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| (data & IEEE_SW_MASK));
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data = (data & FPCR_DYN_MASK) | ieee_swcr_to_fpcr(data);
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}
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*get_reg_addr(task, regno) = data;
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return 0;
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}
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static inline int
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read_int(struct task_struct *task, unsigned long addr, int * data)
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{
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int copied = access_process_vm(task, addr, data, sizeof(int), 0);
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return (copied == sizeof(int)) ? 0 : -EIO;
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}
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static inline int
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write_int(struct task_struct *task, unsigned long addr, int data)
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{
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int copied = access_process_vm(task, addr, &data, sizeof(int), 1);
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return (copied == sizeof(int)) ? 0 : -EIO;
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}
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/*
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* Set breakpoint.
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*/
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int
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ptrace_set_bpt(struct task_struct * child)
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{
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int displ, i, res, reg_b, nsaved = 0;
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unsigned int insn, op_code;
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unsigned long pc;
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pc = get_reg(child, REG_PC);
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res = read_int(child, pc, (int *) &insn);
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if (res < 0)
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return res;
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op_code = insn >> 26;
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if (op_code >= 0x30) {
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/*
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* It's a branch: instead of trying to figure out
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* whether the branch will be taken or not, we'll put
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* a breakpoint at either location. This is simpler,
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* more reliable, and probably not a whole lot slower
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* than the alternative approach of emulating the
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* branch (emulation can be tricky for fp branches).
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*/
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displ = ((s32)(insn << 11)) >> 9;
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task_thread_info(child)->bpt_addr[nsaved++] = pc + 4;
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if (displ) /* guard against unoptimized code */
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task_thread_info(child)->bpt_addr[nsaved++]
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= pc + 4 + displ;
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DBG(DBG_BPT, ("execing branch\n"));
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} else if (op_code == 0x1a) {
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reg_b = (insn >> 16) & 0x1f;
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task_thread_info(child)->bpt_addr[nsaved++] = get_reg(child, reg_b);
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DBG(DBG_BPT, ("execing jump\n"));
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} else {
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task_thread_info(child)->bpt_addr[nsaved++] = pc + 4;
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DBG(DBG_BPT, ("execing normal insn\n"));
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}
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/* install breakpoints: */
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for (i = 0; i < nsaved; ++i) {
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res = read_int(child, task_thread_info(child)->bpt_addr[i],
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(int *) &insn);
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if (res < 0)
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return res;
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task_thread_info(child)->bpt_insn[i] = insn;
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DBG(DBG_BPT, (" -> next_pc=%lx\n",
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task_thread_info(child)->bpt_addr[i]));
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res = write_int(child, task_thread_info(child)->bpt_addr[i],
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BREAKINST);
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if (res < 0)
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return res;
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}
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task_thread_info(child)->bpt_nsaved = nsaved;
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return 0;
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}
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/*
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* Ensure no single-step breakpoint is pending. Returns non-zero
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* value if child was being single-stepped.
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*/
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int
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ptrace_cancel_bpt(struct task_struct * child)
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{
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int i, nsaved = task_thread_info(child)->bpt_nsaved;
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task_thread_info(child)->bpt_nsaved = 0;
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if (nsaved > 2) {
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printk("ptrace_cancel_bpt: bogus nsaved: %d!\n", nsaved);
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nsaved = 2;
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}
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for (i = 0; i < nsaved; ++i) {
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write_int(child, task_thread_info(child)->bpt_addr[i],
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task_thread_info(child)->bpt_insn[i]);
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}
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return (nsaved != 0);
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}
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void user_enable_single_step(struct task_struct *child)
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{
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/* Mark single stepping. */
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task_thread_info(child)->bpt_nsaved = -1;
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}
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void user_disable_single_step(struct task_struct *child)
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{
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ptrace_cancel_bpt(child);
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}
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/*
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* Called by kernel/ptrace.c when detaching..
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*
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* Make sure the single step bit is not set.
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*/
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void ptrace_disable(struct task_struct *child)
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{
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user_disable_single_step(child);
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}
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long arch_ptrace(struct task_struct *child, long request,
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unsigned long addr, unsigned long data)
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{
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unsigned long tmp;
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size_t copied;
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long ret;
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switch (request) {
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/* When I and D space are separate, these will need to be fixed. */
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case PTRACE_PEEKTEXT: /* read word at location addr. */
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case PTRACE_PEEKDATA:
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copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0);
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ret = -EIO;
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if (copied != sizeof(tmp))
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break;
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force_successful_syscall_return();
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ret = tmp;
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break;
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/* Read register number ADDR. */
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case PTRACE_PEEKUSR:
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force_successful_syscall_return();
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ret = get_reg(child, addr);
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DBG(DBG_MEM, ("peek $%lu->%#lx\n", addr, ret));
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break;
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/* When I and D space are separate, this will have to be fixed. */
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case PTRACE_POKETEXT: /* write the word at location addr. */
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case PTRACE_POKEDATA:
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ret = generic_ptrace_pokedata(child, addr, data);
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break;
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case PTRACE_POKEUSR: /* write the specified register */
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DBG(DBG_MEM, ("poke $%lu<-%#lx\n", addr, data));
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ret = put_reg(child, addr, data);
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break;
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default:
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ret = ptrace_request(child, request, addr, data);
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break;
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}
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return ret;
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}
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asmlinkage void
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syscall_trace(void)
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{
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if (!test_thread_flag(TIF_SYSCALL_TRACE))
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return;
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if (!(current->ptrace & PT_PTRACED))
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return;
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/* The 0x80 provides a way for the tracing parent to distinguish
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between a syscall stop and SIGTRAP delivery */
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ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
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? 0x80 : 0));
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/*
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* This isn't the same as continuing with a signal, but it will do
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* for normal use. strace only continues with a signal if the
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* stopping signal is not SIGTRAP. -brl
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*/
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if (current->exit_code) {
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send_sig(current->exit_code, current, 1);
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current->exit_code = 0;
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}
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}
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