linux/drivers/gpu
Akash Goel 24f3a8cf77 drm/i915: Added write-enable pte bit supportt
This adds support for a write-enable bit in the entry of GTT.
This is handled via a read-only flag in the GEM buffer object which
is then used to see how to set the bit when writing the GTT entries.
Currently by default the Batch buffer & Ring buffers are marked as read only.

v2: Moved the pte override code for read-only bit to 'byt_pte_encode'. (Chris)
    Fixed the issue of leaving 'gt_old_ro' as unused. (Chris)

v3: Removed the 'gt_old_ro' field, now setting RO bit only for Ring Buffers(Daniel).

v4: Added a new 'flags' parameter to all the pte(gen6) encode & insert_entries functions,
    in lieu of overloading the cache_level enum (Daniel).

v5: Removed the superfluous VLV check & changed the definition location of PTE_READ_ONLY flag (Imre)

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-06-17 09:21:47 +02:00
..
drm drm/i915: Added write-enable pte bit supportt 2014-06-17 09:21:47 +02:00
host1x gpu: host1x: Rename internal functions for clarity 2014-06-05 23:10:30 +02:00
ipu-v3 gpu: ipu-v3: Register the CSI modules 2014-06-04 11:07:12 +02:00
vga vgaswitcheroo: switch the mux to the igp on power down when runpm is enabled 2014-06-02 10:25:08 -04:00
Makefile gpu: ipu-v3: Move i.MX IPUv3 core driver out of staging 2014-06-04 11:06:52 +02:00