597ce1723e
CPUs implementing MIPS32 R2 may include a 64-bit FPU, just as MIPS64 CPUs do. In order to preserve backwards compatibility a 64-bit FPU will act like a 32-bit FPU (by accessing doubles from the least significant 32 bits of an even-odd pair of FP registers) when the Status.FR bit is zero, again just like a mips64 CPU. The standard O32 ABI is defined expecting a 32-bit FPU, however recent toolchains support use of a 64-bit FPU from an O32 MIPS32 executable. When an ELF executable is built to use a 64-bit FPU a new flag (EF_MIPS_FP64) is set in the ELF header. With this patch the kernel will check the EF_MIPS_FP64 flag when executing an O32 binary, and set Status.FR accordingly. The addition of O32 64-bit FP support lessens the opportunity for optimisation in the FPU emulator, so a CONFIG_MIPS_O32_FP64_SUPPORT Kconfig option is introduced to allow this support to be disabled for those that don't require it. Inspired by an earlier patch by Leonid Yegoshin, but implemented more cleanly & correctly. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6154/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
187 lines
5.8 KiB
C
187 lines
5.8 KiB
C
/* thread_info.h: MIPS low-level thread information
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*
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* Copyright (C) 2002 David Howells (dhowells@redhat.com)
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* - Incorporating suggestions made by Linus Torvalds and Dave Miller
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*/
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#ifndef _ASM_THREAD_INFO_H
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#define _ASM_THREAD_INFO_H
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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#include <asm/processor.h>
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/*
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* low level task data that entry.S needs immediate access to
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* - this struct should fit entirely inside of one cache line
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* - this struct shares the supervisor stack pages
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* - if the contents of this structure are changed, the assembly constants
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* must also be changed
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*/
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struct thread_info {
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struct task_struct *task; /* main task structure */
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struct exec_domain *exec_domain; /* execution domain */
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unsigned long flags; /* low level flags */
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unsigned long tp_value; /* thread pointer */
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__u32 cpu; /* current CPU */
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int preempt_count; /* 0 => preemptable, <0 => BUG */
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mm_segment_t addr_limit; /*
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* thread address space limit:
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* 0x7fffffff for user-thead
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* 0xffffffff for kernel-thread
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*/
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struct restart_block restart_block;
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struct pt_regs *regs;
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};
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/*
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* macros/functions for gaining access to the thread information structure
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*/
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#define INIT_THREAD_INFO(tsk) \
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{ \
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.task = &tsk, \
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.exec_domain = &default_exec_domain, \
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.flags = _TIF_FIXADE, \
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.cpu = 0, \
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.preempt_count = INIT_PREEMPT_COUNT, \
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.addr_limit = KERNEL_DS, \
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.restart_block = { \
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.fn = do_no_restart_syscall, \
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}, \
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}
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#define init_thread_info (init_thread_union.thread_info)
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#define init_stack (init_thread_union.stack)
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/* How to get the thread information struct from C. */
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static inline struct thread_info *current_thread_info(void)
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{
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register struct thread_info *__current_thread_info __asm__("$28");
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return __current_thread_info;
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}
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#endif /* !__ASSEMBLY__ */
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/* thread information allocation */
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#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT)
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#define THREAD_SIZE_ORDER (1)
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#endif
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#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_64BIT)
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#define THREAD_SIZE_ORDER (2)
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#endif
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#ifdef CONFIG_PAGE_SIZE_8KB
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#define THREAD_SIZE_ORDER (1)
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#endif
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#ifdef CONFIG_PAGE_SIZE_16KB
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#define THREAD_SIZE_ORDER (0)
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#endif
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#ifdef CONFIG_PAGE_SIZE_32KB
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#define THREAD_SIZE_ORDER (0)
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#endif
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#ifdef CONFIG_PAGE_SIZE_64KB
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#define THREAD_SIZE_ORDER (0)
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#endif
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#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
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#define THREAD_MASK (THREAD_SIZE - 1UL)
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#define STACK_WARN (THREAD_SIZE / 8)
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/*
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* thread information flags
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* - these are process state flags that various assembly files may need to
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* access
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* - pending work-to-be-done flags are in LSW
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* - other flags in MSW
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*/
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#define TIF_SIGPENDING 1 /* signal pending */
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#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
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#define TIF_SYSCALL_AUDIT 3 /* syscall auditing active */
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#define TIF_SECCOMP 4 /* secure computing */
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#define TIF_NOTIFY_RESUME 5 /* callback before returning to user */
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#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */
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#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */
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#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
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#define TIF_NOHZ 19 /* in adaptive nohz mode */
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#define TIF_FIXADE 20 /* Fix address errors in software */
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#define TIF_LOGADE 21 /* Log address errors to syslog */
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#define TIF_32BIT_REGS 22 /* 32-bit general purpose registers */
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#define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */
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#define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */
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#define TIF_LOAD_WATCH 25 /* If set, load watch registers */
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#define TIF_SYSCALL_TRACEPOINT 26 /* syscall tracepoint instrumentation */
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#define TIF_32BIT_FPREGS 27 /* 32-bit floating point registers */
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#define TIF_SYSCALL_TRACE 31 /* syscall trace active */
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#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
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#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
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#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
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#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
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#define _TIF_SECCOMP (1<<TIF_SECCOMP)
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#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
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#define _TIF_USEDFPU (1<<TIF_USEDFPU)
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#define _TIF_NOHZ (1<<TIF_NOHZ)
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#define _TIF_FIXADE (1<<TIF_FIXADE)
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#define _TIF_LOGADE (1<<TIF_LOGADE)
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#define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS)
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#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR)
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#define _TIF_FPUBOUND (1<<TIF_FPUBOUND)
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#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH)
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#define _TIF_32BIT_FPREGS (1<<TIF_32BIT_FPREGS)
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#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
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#define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \
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_TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT)
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/* work to do in syscall_trace_leave() */
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#define _TIF_WORK_SYSCALL_EXIT (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \
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_TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT)
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/* work to do on interrupt/exception return */
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#define _TIF_WORK_MASK \
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(_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME)
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/* work to do on any return to u-space */
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#define _TIF_ALLWORK_MASK (_TIF_NOHZ | _TIF_WORK_MASK | \
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_TIF_WORK_SYSCALL_EXIT | \
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_TIF_SYSCALL_TRACEPOINT)
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/*
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* We stash processor id into a COP0 register to retrieve it fast
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* at kernel exception entry.
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*/
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#if defined(CONFIG_MIPS_MT_SMTC)
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#define SMP_CPUID_REG 2, 2 /* TCBIND */
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#define ASM_SMP_CPUID_REG $2, 2
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#define SMP_CPUID_PTRSHIFT 19
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#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
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#define SMP_CPUID_REG 20, 0 /* XCONTEXT */
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#define ASM_SMP_CPUID_REG $20
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#define SMP_CPUID_PTRSHIFT 48
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#else
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#define SMP_CPUID_REG 4, 0 /* CONTEXT */
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#define ASM_SMP_CPUID_REG $4
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#define SMP_CPUID_PTRSHIFT 23
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#endif
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#ifdef CONFIG_64BIT
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#define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 3)
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#else
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#define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 2)
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#endif
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#ifdef CONFIG_MIPS_MT_SMTC
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#define ASM_CPUID_MFC0 mfc0
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#define UASM_i_CPUID_MFC0 uasm_i_mfc0
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#else
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#define ASM_CPUID_MFC0 MFC0
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#define UASM_i_CPUID_MFC0 UASM_i_MFC0
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#endif
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#endif /* __KERNEL__ */
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#endif /* _ASM_THREAD_INFO_H */
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