Wesley Chalmers 39a1355fef drm/amd/display: Add interface for ADD & DROP PIXEL Registers ...

[WHY]
HW has handed down a new sequence that requires access to these
registers.

v2: squash in DCN3.1 fixes (Alex)

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2021-06-08 12:22:42 -04:00

..

abm.h

drm/amd/display: Added support for individual control for multiple back-light instances.

2021-05-27 12:24:03 -04:00

audio.h

drm/amd/display: Disable audio stream only if it's currently enabled

2019-05-31 10:39:30 -05:00

aux_engine.h

drm/amd/display: Support for DMUB AUX

2021-03-02 14:05:41 -05:00

clk_mgr_internal.h

drm/amd/display: Simplify bool comparison

2021-02-09 15:49:42 -05:00

clk_mgr.h

drm/amd/display: Add DCN3.1 clock manager support

2021-06-04 16:03:26 -04:00

dccg.h

drm/amd/display: Add interface for ADD & DROP PIXEL Registers

2021-06-08 12:22:42 -04:00

dchubbub.h

drm/amd/display: Add DCN3.1 DCHHUB

2021-06-04 16:39:18 -04:00

dmcu.h

drm/amd/display: Process crc window at DMCU

2021-03-05 15:11:54 -05:00

dpp.h

drm/amd/display: Document set RECOUT operation

2021-05-19 22:38:56 -04:00

dsc.h

drm/amd/display: add dsc stream overhead for dp only

2021-05-10 18:06:44 -04:00

dwb.h

drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)

2020-11-04 17:11:37 -05:00

gpio.h

drm/amd/display: refactor gpio to allocate hw_container in constructor

2019-08-15 10:53:55 -05:00

hubp.h

drm/amd/display: Set max TTU on DPG enable

2021-04-09 16:48:53 -04:00

hw_shared.h

drm/amd/display: Update link encoder object creation

2021-03-02 14:05:52 -05:00

ipp.h

drm/amd/display: csc_transform to dc_csc_transform

2018-05-15 13:42:54 -05:00

link_encoder.h

drm/amd/display: Add DCN3.1 DIO

2021-06-04 16:39:18 -04:00

mcif_wb.h

drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)

2020-11-04 17:11:37 -05:00

mem_input.h

drm/amd/display: Add DCN3.1 DCHHUB

2021-06-04 16:39:18 -04:00

mpc.h

drm/amd/display: Refactor visual confirm

2021-06-08 12:18:37 -04:00

opp.h

drm/amd/display: Raise DPG height during timing synchronization

2020-10-26 13:29:21 -04:00

panel_cntl.h

drm/amd/display: Add read backlight interface

2020-08-17 14:08:12 -04:00

stream_encoder.h

drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)

2020-11-04 17:11:37 -05:00

timing_generator.h

drm/amd/display: Return last used DRR VTOTAL from DC

2021-06-08 12:20:12 -04:00

transform.h

drm/amd/display: fix odm scaling

2021-05-27 12:26:17 -04:00

vmid.h

drm/amd/display: move vmid determination logic to a module

2019-06-22 09:34:14 -05:00