forked from Minki/linux
f1a26fdf59
The MinnowBoard uses an AR803x PHY with the PCH GBE which requires special handling. Use the MinnowBoard PCI Subsystem ID to detect this and add a pci_device_id.driver_data structure and functions to handle platform setup. The AR803x does not implement the RGMII 2ns TX clock delay in the trace routing nor via strapping. Add a detection method for the board and the PHY and enable the TX clock delay via the registers. This PHY will hibernate without link for 10 seconds. Ensure the PHY is awake for probe and then disable hibernation. A future improvement would be to convert pch_gbe to using PHYLIB and making sure we can wake the PHY at the necessary times rather than permanently disabling it. Signed-off-by: Darren Hart <dvhart@linux.intel.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Peter Waskiewicz <peter.p.waskiewicz.jr@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Joe Perches <joe@perches.com> Cc: netdev@vger.kernel.org
39 lines
1.5 KiB
C
39 lines
1.5 KiB
C
/*
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* Copyright (C) 1999 - 2010 Intel Corporation.
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* Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
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*
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* This code was derived from the Intel e1000e Linux driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef _PCH_GBE_PHY_H_
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#define _PCH_GBE_PHY_H_
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#define PCH_GBE_PHY_REGS_LEN 32
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#define PCH_GBE_PHY_RESET_DELAY_US 10
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#define PCH_GBE_MAC_IFOP_RGMII
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s32 pch_gbe_phy_get_id(struct pch_gbe_hw *hw);
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s32 pch_gbe_phy_read_reg_miic(struct pch_gbe_hw *hw, u32 offset, u16 *data);
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s32 pch_gbe_phy_write_reg_miic(struct pch_gbe_hw *hw, u32 offset, u16 data);
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void pch_gbe_phy_sw_reset(struct pch_gbe_hw *hw);
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void pch_gbe_phy_hw_reset(struct pch_gbe_hw *hw);
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void pch_gbe_phy_power_up(struct pch_gbe_hw *hw);
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void pch_gbe_phy_power_down(struct pch_gbe_hw *hw);
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void pch_gbe_phy_set_rgmii(struct pch_gbe_hw *hw);
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void pch_gbe_phy_init_setting(struct pch_gbe_hw *hw);
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int pch_gbe_phy_disable_hibernate(struct pch_gbe_hw *hw);
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#endif /* _PCH_GBE_PHY_H_ */
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