Stephen Warren 22bd1f7ef4 ARM: dt: tegra seaboard: fix I2C2 SCL rate ... This I2C bus is used for EDID/DDC reads and other "slow" I2C devices. This requires a 100KHz SCL (clock) rate. Signed-off-by: Stephen Warren <swarren@nvidia.com>		2012-05-03 14:49:08 -06:00
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bootp	ARM: 6499/1: Thumb-2: Correct data alignment for CONFIG_THUMB2_KERNEL in bootp/init.S	2010-11-30 13:44:24 +00:00
compressed	ARM: 7380/1: DT: do not add a zero-sized memory property	2012-04-13 14:05:41 +01:00
dts	ARM: dt: tegra seaboard: fix I2C2 SCL rate	2012-05-03 14:49:08 -06:00
.gitignore	ARM: devicetree: Add .dtb files to arch/arm/boot/.gitignore	2012-01-30 11:47:37 -07:00
install.sh	kbuild: use INSTALLKERNEL to select customized installkernel script	2009-09-20 12:18:14 +02:00
Makefile	Kbuild: centralize MKIMAGE and cmd_uimage definitions	2012-03-26 15:49:20 +02:00