54b879b76e
Different platform may have different number of lanes for the UFS link. Add parameter to device tree specifying how many lanes should be configured for the UFS link. Reviewed-by: Hannes Reinecke <hare@suse.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gilad Broner <gbroner@codeaurora.org> Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
70 lines
3.0 KiB
Plaintext
70 lines
3.0 KiB
Plaintext
* Universal Flash Storage (UFS) Host Controller
|
|
|
|
UFSHC nodes are defined to describe on-chip UFS host controllers.
|
|
Each UFS controller instance should have its own node.
|
|
|
|
Required properties:
|
|
- compatible : must contain "jedec,ufs-1.1", may also list one or more
|
|
of the following:
|
|
"qcom,msm8994-ufshc"
|
|
"qcom,msm8996-ufshc"
|
|
"qcom,ufshc"
|
|
- interrupts : <interrupt mapping for UFS host controller IRQ>
|
|
- reg : <registers mapping>
|
|
|
|
Optional properties:
|
|
- phys : phandle to UFS PHY node
|
|
- phy-names : the string "ufsphy" when is found in a node, along
|
|
with "phys" attribute, provides phandle to UFS PHY node
|
|
- vdd-hba-supply : phandle to UFS host controller supply regulator node
|
|
- vcc-supply : phandle to VCC supply regulator node
|
|
- vccq-supply : phandle to VCCQ supply regulator node
|
|
- vccq2-supply : phandle to VCCQ2 supply regulator node
|
|
- vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V
|
|
or 2.7-3.6V. This boolean property when set, specifies
|
|
to use low voltage range of 1.7-1.95V. Note for external
|
|
UFS cards this property is invalid and valid VCC range is
|
|
always 2.7-3.6V.
|
|
- vcc-max-microamp : specifies max. load that can be drawn from vcc supply
|
|
- vccq-max-microamp : specifies max. load that can be drawn from vccq supply
|
|
- vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply
|
|
- <name>-fixed-regulator : boolean property specifying that <name>-supply is a fixed regulator
|
|
|
|
- clocks : List of phandle and clock specifier pairs
|
|
- clock-names : List of clock input name strings sorted in the same
|
|
order as the clocks property.
|
|
- freq-table-hz : Array of <min max> operating frequencies stored in the same
|
|
order as the clocks property. If this property is not
|
|
defined or a value in the array is "0" then it is assumed
|
|
that the frequency is set by the parent clock or a
|
|
fixed rate clock source.
|
|
-lanes-per-direction : number of lanes available per direction - either 1 or 2.
|
|
Note that it is assume same number of lanes is used both
|
|
directions at once. If not specified, default is 2 lanes per direction.
|
|
|
|
Note: If above properties are not defined it can be assumed that the supply
|
|
regulators or clocks are always on.
|
|
|
|
Example:
|
|
ufshc@0xfc598000 {
|
|
compatible = "jedec,ufs-1.1";
|
|
reg = <0xfc598000 0x800>;
|
|
interrupts = <0 28 0>;
|
|
|
|
vdd-hba-supply = <&xxx_reg0>;
|
|
vdd-hba-fixed-regulator;
|
|
vcc-supply = <&xxx_reg1>;
|
|
vcc-supply-1p8;
|
|
vccq-supply = <&xxx_reg2>;
|
|
vccq2-supply = <&xxx_reg3>;
|
|
vcc-max-microamp = 500000;
|
|
vccq-max-microamp = 200000;
|
|
vccq2-max-microamp = 200000;
|
|
|
|
clocks = <&core 0>, <&ref 0>, <&iface 0>;
|
|
clock-names = "core_clk", "ref_clk", "iface_clk";
|
|
freq-table-hz = <100000000 200000000>, <0 0>, <0 0>;
|
|
phys = <&ufsphy1>;
|
|
phy-names = "ufsphy";
|
|
};
|