e75d1b2c37
There's no reason for treating DCB as first class citizen when configuring the Tx queues and going through TCs. Reverse the logic and base the configuration logic on rings, which is the object of interest anyway. Signed-off-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
32 lines
1.1 KiB
C
32 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2019, Intel Corporation. */
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#ifndef _ICE_BASE_H_
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#define _ICE_BASE_H_
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#include "ice.h"
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int ice_setup_rx_ctx(struct ice_ring *ring);
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int __ice_vsi_get_qs(struct ice_qs_cfg *qs_cfg);
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int ice_vsi_ctrl_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx);
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int ice_vsi_alloc_q_vectors(struct ice_vsi *vsi);
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void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi);
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void ice_vsi_free_q_vectors(struct ice_vsi *vsi);
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int
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ice_vsi_cfg_txq(struct ice_vsi *vsi, struct ice_ring *ring,
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struct ice_aqc_add_tx_qgrp *qg_buf);
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void ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector);
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void
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ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx);
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void
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ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx);
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void ice_trigger_sw_intr(struct ice_hw *hw, struct ice_q_vector *q_vector);
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int
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ice_vsi_stop_tx_ring(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,
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u16 rel_vmvf_num, struct ice_ring *ring,
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struct ice_txq_meta *txq_meta);
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void
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ice_fill_txq_meta(struct ice_vsi *vsi, struct ice_ring *ring,
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struct ice_txq_meta *txq_meta);
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#endif /* _ICE_BASE_H_ */
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