forked from Minki/linux
9a9952bbd7
This time the IOMMU updates are mostly cleanups or fixes. No big new features or drivers this time. In particular the changes include: * Bigger cleanup of the Domain<->IOMMU data structures and the code that manages them in the Intel VT-d driver. This makes the code easier to understand and maintain, and also easier to keep the data structures in sync. It is also a preparation step to make use of default domains from the IOMMU core in the Intel VT-d driver. * Fixes for a couple of DMA-API misuses in ARM IOMMU drivers, namely in the ARM and Tegra SMMU drivers. * Fix for a potential buffer overflow in the OMAP iommu driver's debug code * A couple of smaller fixes and cleanups in various drivers * One small new feature: Report domain-id usage in the Intel VT-d driver to easier detect bugs where these are leaked. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABAgAGBQJV7sCEAAoJECvwRC2XARrjz3YP/Au4IIfqykfPvmI0cmPhVnAV Q72tltwkbK2u2iP+pHheveaMngJtAshsZrnhBon4KJRIt/KTLZQvsFplHDaRhPfY yw3LIxhC5kLG/S6irY9Ozb0+uTMdQ3BU2uS23pyoFVfCz+RngBrAwDBcTKqZDCDG 8dNd+T21XlzxuyeGr58h9upz2VFtq6feoGFhLU5PNxTlf4JWZe77D7NlbSvx6Nwy 7Ai8dVRgpV9ciUP7w8FXrCUvbMZQDIoTMiWGNSlogVMgA0dllGES91UZYhWf3pil abuX6DeFul/cOhEOnH2xa+j5zz2O/upe9stU4wAFw6IhPiAELTHc2NKlWAhwb0SY bpDRf7dgLnUfqpmZLpWjTwN4jllc0qS2MIHj+eUu0uhdFi4Z0BuH2wSCdbR7xkqk u5u0Jq7hDNKs5FmQTSsWSiAdjakMsRjIN7jMrBbOeZnBSmUnLx74KGPLTb63ncR3 WIOi4Iyu+LSXBIvZDiLu3lIIh7Atzd+y7IDnb8KXdyqfy+h53OZZOJNbP/qTWHgT ZUdm/qrqjIQpTQfleOEadC7vY/y3fR5sBtOQHUamfntni3oYCc4AMRlNdf3eV9lb Tyss6F699mU7d/vennTaIToBgVwaXdLYtmvGWjnoT/kqOMclyDf3cIUtZGtp2rJR ddmzDA3vBUC5pGj8Hd8R =yoGE -----END PGP SIGNATURE----- Merge tag 'iommu-updates-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull iommu updates for from Joerg Roedel: "This time the IOMMU updates are mostly cleanups or fixes. No big new features or drivers this time. In particular the changes include: - Bigger cleanup of the Domain<->IOMMU data structures and the code that manages them in the Intel VT-d driver. This makes the code easier to understand and maintain, and also easier to keep the data structures in sync. It is also a preparation step to make use of default domains from the IOMMU core in the Intel VT-d driver. - Fixes for a couple of DMA-API misuses in ARM IOMMU drivers, namely in the ARM and Tegra SMMU drivers. - Fix for a potential buffer overflow in the OMAP iommu driver's debug code - A couple of smaller fixes and cleanups in various drivers - One small new feature: Report domain-id usage in the Intel VT-d driver to easier detect bugs where these are leaked" * tag 'iommu-updates-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (83 commits) iommu/vt-d: Really use upper context table when necessary x86/vt-d: Fix documentation of DRHD iommu/fsl: Really fix init section(s) content iommu/io-pgtable-arm: Unmap and free table when overwriting with block iommu/io-pgtable-arm: Move init-fn declarations to io-pgtable.h iommu/msm: Use BUG_ON instead of if () BUG() iommu/vt-d: Access iomem correctly iommu/vt-d: Make two functions static iommu/vt-d: Use BUG_ON instead of if () BUG() iommu/vt-d: Return false instead of 0 in irq_remapping_cap() iommu/amd: Use BUG_ON instead of if () BUG() iommu/amd: Make a symbol static iommu/amd: Simplify allocation in irq_remapping_alloc() iommu/tegra-smmu: Parameterize number of TLB lines iommu/tegra-smmu: Factor out tegra_smmu_set_pde() iommu/tegra-smmu: Extract tegra_smmu_pte_get_use() iommu/tegra-smmu: Use __GFP_ZERO to allocate zeroed pages iommu/tegra-smmu: Remove PageReserved manipulation iommu/tegra-smmu: Convert to use DMA API iommu/tegra-smmu: smmu_flush_ptc() wants device addresses ...
373 lines
10 KiB
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373 lines
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Plaintext
# IOMMU_API always gets selected by whoever wants it.
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config IOMMU_API
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bool
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menuconfig IOMMU_SUPPORT
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bool "IOMMU Hardware Support"
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depends on MMU
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default y
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---help---
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Say Y here if you want to compile device drivers for IO Memory
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Management Units into the kernel. These devices usually allow to
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remap DMA requests and/or remap interrupts from other devices on the
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system.
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if IOMMU_SUPPORT
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menu "Generic IOMMU Pagetable Support"
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# Selected by the actual pagetable implementations
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config IOMMU_IO_PGTABLE
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bool
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config IOMMU_IO_PGTABLE_LPAE
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bool "ARMv7/v8 Long Descriptor Format"
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select IOMMU_IO_PGTABLE
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# SWIOTLB guarantees a dma_to_phys() implementation
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depends on ARM || ARM64 || (COMPILE_TEST && SWIOTLB)
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help
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Enable support for the ARM long descriptor pagetable format.
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This allocator supports 4K/2M/1G, 16K/32M and 64K/512M page
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sizes at both stage-1 and stage-2, as well as address spaces
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up to 48-bits in size.
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config IOMMU_IO_PGTABLE_LPAE_SELFTEST
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bool "LPAE selftests"
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depends on IOMMU_IO_PGTABLE_LPAE
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help
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Enable self-tests for LPAE page table allocator. This performs
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a series of page-table consistency checks during boot.
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If unsure, say N here.
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endmenu
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config IOMMU_IOVA
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bool
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config OF_IOMMU
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def_bool y
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depends on OF && IOMMU_API
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config FSL_PAMU
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bool "Freescale IOMMU support"
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depends on PPC32
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depends on PPC_E500MC || COMPILE_TEST
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select IOMMU_API
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select GENERIC_ALLOCATOR
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help
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Freescale PAMU support. PAMU is the IOMMU present on Freescale QorIQ platforms.
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PAMU can authorize memory access, remap the memory address, and remap I/O
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transaction types.
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# MSM IOMMU support
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config MSM_IOMMU
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bool "MSM IOMMU Support"
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depends on ARM
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depends on ARCH_MSM8X60 || ARCH_MSM8960 || COMPILE_TEST
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depends on BROKEN
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select IOMMU_API
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help
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Support for the IOMMUs found on certain Qualcomm SOCs.
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These IOMMUs allow virtualization of the address space used by most
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cores within the multimedia subsystem.
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If unsure, say N here.
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config IOMMU_PGTABLES_L2
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def_bool y
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depends on MSM_IOMMU && MMU && SMP && CPU_DCACHE_DISABLE=n
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# AMD IOMMU support
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config AMD_IOMMU
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bool "AMD IOMMU support"
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select SWIOTLB
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select PCI_MSI
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select PCI_ATS
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select PCI_PRI
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select PCI_PASID
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select IOMMU_API
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depends on X86_64 && PCI && ACPI
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---help---
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With this option you can enable support for AMD IOMMU hardware in
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your system. An IOMMU is a hardware component which provides
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remapping of DMA memory accesses from devices. With an AMD IOMMU you
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can isolate the DMA memory of different devices and protect the
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system from misbehaving device drivers or hardware.
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You can find out if your system has an AMD IOMMU if you look into
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your BIOS for an option to enable it or if you have an IVRS ACPI
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table.
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config AMD_IOMMU_STATS
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bool "Export AMD IOMMU statistics to debugfs"
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depends on AMD_IOMMU
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select DEBUG_FS
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---help---
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This option enables code in the AMD IOMMU driver to collect various
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statistics about whats happening in the driver and exports that
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information to userspace via debugfs.
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If unsure, say N.
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config AMD_IOMMU_V2
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tristate "AMD IOMMU Version 2 driver"
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depends on AMD_IOMMU
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select MMU_NOTIFIER
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---help---
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This option enables support for the AMD IOMMUv2 features of the IOMMU
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hardware. Select this option if you want to use devices that support
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the PCI PRI and PASID interface.
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# Intel IOMMU support
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config DMAR_TABLE
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bool
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config INTEL_IOMMU
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bool "Support for Intel IOMMU using DMA Remapping Devices"
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depends on PCI_MSI && ACPI && (X86 || IA64_GENERIC)
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select IOMMU_API
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select IOMMU_IOVA
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select DMAR_TABLE
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help
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DMA remapping (DMAR) devices support enables independent address
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translations for Direct Memory Access (DMA) from devices.
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These DMA remapping devices are reported via ACPI tables
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and include PCI device scope covered by these DMA
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remapping devices.
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config INTEL_IOMMU_DEFAULT_ON
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def_bool y
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prompt "Enable Intel DMA Remapping Devices by default"
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depends on INTEL_IOMMU
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help
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Selecting this option will enable a DMAR device at boot time if
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one is found. If this option is not selected, DMAR support can
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be enabled by passing intel_iommu=on to the kernel.
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config INTEL_IOMMU_BROKEN_GFX_WA
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bool "Workaround broken graphics drivers (going away soon)"
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depends on INTEL_IOMMU && BROKEN && X86
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---help---
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Current Graphics drivers tend to use physical address
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for DMA and avoid using DMA APIs. Setting this config
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option permits the IOMMU driver to set a unity map for
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all the OS-visible memory. Hence the driver can continue
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to use physical addresses for DMA, at least until this
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option is removed in the 2.6.32 kernel.
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config INTEL_IOMMU_FLOPPY_WA
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def_bool y
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depends on INTEL_IOMMU && X86
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---help---
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Floppy disk drivers are known to bypass DMA API calls
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thereby failing to work when IOMMU is enabled. This
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workaround will setup a 1:1 mapping for the first
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16MiB to make floppy (an ISA device) work.
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config IRQ_REMAP
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bool "Support for Interrupt Remapping"
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depends on X86_64 && X86_IO_APIC && PCI_MSI && ACPI
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select DMAR_TABLE
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---help---
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Supports Interrupt remapping for IO-APIC and MSI devices.
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To use x2apic mode in the CPU's which support x2APIC enhancements or
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to support platforms with CPU's having > 8 bit APIC ID, say Y.
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# OMAP IOMMU support
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config OMAP_IOMMU
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bool "OMAP IOMMU Support"
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depends on ARM && MMU
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depends on ARCH_OMAP2PLUS || COMPILE_TEST
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select IOMMU_API
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---help---
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The OMAP3 media platform drivers depend on iommu support,
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if you need them say Y here.
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config OMAP_IOMMU_DEBUG
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bool "Export OMAP IOMMU internals in DebugFS"
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depends on OMAP_IOMMU && DEBUG_FS
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---help---
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Select this to see extensive information about
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the internal state of OMAP IOMMU in debugfs.
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Say N unless you know you need this.
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config ROCKCHIP_IOMMU
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bool "Rockchip IOMMU Support"
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depends on ARM
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depends on ARCH_ROCKCHIP || COMPILE_TEST
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select IOMMU_API
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select ARM_DMA_USE_IOMMU
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help
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Support for IOMMUs found on Rockchip rk32xx SOCs.
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These IOMMUs allow virtualization of the address space used by most
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cores within the multimedia subsystem.
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Say Y here if you are using a Rockchip SoC that includes an IOMMU
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device.
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config TEGRA_IOMMU_GART
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bool "Tegra GART IOMMU Support"
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depends on ARCH_TEGRA_2x_SOC
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select IOMMU_API
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help
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Enables support for remapping discontiguous physical memory
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shared with the operating system into contiguous I/O virtual
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space through the GART (Graphics Address Relocation Table)
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hardware included on Tegra SoCs.
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config TEGRA_IOMMU_SMMU
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bool "NVIDIA Tegra SMMU Support"
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depends on ARCH_TEGRA
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depends on TEGRA_AHB
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depends on TEGRA_MC
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select IOMMU_API
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help
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This driver supports the IOMMU hardware (SMMU) found on NVIDIA Tegra
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SoCs (Tegra30 up to Tegra210).
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config EXYNOS_IOMMU
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bool "Exynos IOMMU Support"
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depends on ARCH_EXYNOS && ARM && MMU
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select IOMMU_API
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select ARM_DMA_USE_IOMMU
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help
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Support for the IOMMU (System MMU) of Samsung Exynos application
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processor family. This enables H/W multimedia accelerators to see
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non-linear physical memory chunks as linear memory in their
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address space.
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If unsure, say N here.
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config EXYNOS_IOMMU_DEBUG
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bool "Debugging log for Exynos IOMMU"
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depends on EXYNOS_IOMMU
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help
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Select this to see the detailed log message that shows what
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happens in the IOMMU driver.
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Say N unless you need kernel log message for IOMMU debugging.
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config SHMOBILE_IPMMU
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bool
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config SHMOBILE_IPMMU_TLB
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bool
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config SHMOBILE_IOMMU
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bool "IOMMU for Renesas IPMMU/IPMMUI"
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default n
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depends on ARM && MMU
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depends on ARCH_SHMOBILE || COMPILE_TEST
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select IOMMU_API
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select ARM_DMA_USE_IOMMU
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select SHMOBILE_IPMMU
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select SHMOBILE_IPMMU_TLB
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help
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Support for Renesas IPMMU/IPMMUI. This option enables
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remapping of DMA memory accesses from all of the IP blocks
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on the ICB.
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Warning: Drivers (including userspace drivers of UIO
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devices) of the IP blocks on the ICB *must* use addresses
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allocated from the IPMMU (iova) for DMA with this option
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enabled.
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If unsure, say N.
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choice
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prompt "IPMMU/IPMMUI address space size"
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default SHMOBILE_IOMMU_ADDRSIZE_2048MB
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depends on SHMOBILE_IOMMU
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help
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This option sets IPMMU/IPMMUI address space size by
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adjusting the 1st level page table size. The page table size
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is calculated as follows:
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page table size = number of page table entries * 4 bytes
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number of page table entries = address space size / 1 MiB
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For example, when the address space size is 2048 MiB, the
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1st level page table size is 8192 bytes.
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config SHMOBILE_IOMMU_ADDRSIZE_2048MB
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bool "2 GiB"
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config SHMOBILE_IOMMU_ADDRSIZE_1024MB
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bool "1 GiB"
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config SHMOBILE_IOMMU_ADDRSIZE_512MB
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bool "512 MiB"
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config SHMOBILE_IOMMU_ADDRSIZE_256MB
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bool "256 MiB"
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config SHMOBILE_IOMMU_ADDRSIZE_128MB
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bool "128 MiB"
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config SHMOBILE_IOMMU_ADDRSIZE_64MB
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bool "64 MiB"
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config SHMOBILE_IOMMU_ADDRSIZE_32MB
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bool "32 MiB"
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endchoice
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config SHMOBILE_IOMMU_L1SIZE
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int
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default 8192 if SHMOBILE_IOMMU_ADDRSIZE_2048MB
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default 4096 if SHMOBILE_IOMMU_ADDRSIZE_1024MB
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default 2048 if SHMOBILE_IOMMU_ADDRSIZE_512MB
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default 1024 if SHMOBILE_IOMMU_ADDRSIZE_256MB
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default 512 if SHMOBILE_IOMMU_ADDRSIZE_128MB
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default 256 if SHMOBILE_IOMMU_ADDRSIZE_64MB
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default 128 if SHMOBILE_IOMMU_ADDRSIZE_32MB
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config IPMMU_VMSA
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bool "Renesas VMSA-compatible IPMMU"
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depends on ARM_LPAE
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depends on ARCH_SHMOBILE || COMPILE_TEST
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select IOMMU_API
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select IOMMU_IO_PGTABLE_LPAE
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select ARM_DMA_USE_IOMMU
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help
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Support for the Renesas VMSA-compatible IPMMU Renesas found in the
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R-Mobile APE6 and R-Car H2/M2 SoCs.
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If unsure, say N.
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config SPAPR_TCE_IOMMU
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bool "sPAPR TCE IOMMU Support"
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depends on PPC_POWERNV || PPC_PSERIES
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select IOMMU_API
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help
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Enables bits of IOMMU API required by VFIO. The iommu_ops
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is not implemented as it is not necessary for VFIO.
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# ARM IOMMU support
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config ARM_SMMU
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bool "ARM Ltd. System MMU (SMMU) Support"
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depends on (ARM64 || ARM) && MMU
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select IOMMU_API
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select IOMMU_IO_PGTABLE_LPAE
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select ARM_DMA_USE_IOMMU if ARM
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help
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Support for implementations of the ARM System MMU architecture
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versions 1 and 2.
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Say Y here if your SoC includes an IOMMU device implementing
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the ARM SMMU architecture.
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config ARM_SMMU_V3
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bool "ARM Ltd. System MMU Version 3 (SMMUv3) Support"
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depends on ARM64 && PCI
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select IOMMU_API
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select IOMMU_IO_PGTABLE_LPAE
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help
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Support for implementations of the ARM System MMU architecture
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version 3 providing translation support to a PCIe root complex.
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Say Y here if your system includes an IOMMU device implementing
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the ARM SMMUv3 architecture.
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endif # IOMMU_SUPPORT
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