b8c86fc5d8
The SDHCI interface is not PCI specific, yet the Linux driver was intimitely connected to the PCI bus. This patch properly separates the PCI specific portion from the bus independent code. This patch is based on work by Ben Dooks but he did not have time to complete it. Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
1427 lines
34 KiB
C
1427 lines
34 KiB
C
/*
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* linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
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*
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* Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*
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* Thanks to the following companies for their support:
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*
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* - JMicron (hardware and technical support)
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*/
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#include <linux/delay.h>
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#include <linux/highmem.h>
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#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#include <linux/scatterlist.h>
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#include <linux/leds.h>
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#include <linux/mmc/host.h>
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#include "sdhci.h"
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#define DRIVER_NAME "sdhci"
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#define DBG(f, x...) \
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pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
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static unsigned int debug_quirks = 0;
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static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
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static void sdhci_finish_data(struct sdhci_host *);
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static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
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static void sdhci_finish_command(struct sdhci_host *);
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static void sdhci_dumpregs(struct sdhci_host *host)
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{
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printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
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printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
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readl(host->ioaddr + SDHCI_DMA_ADDRESS),
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readw(host->ioaddr + SDHCI_HOST_VERSION));
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printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
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readw(host->ioaddr + SDHCI_BLOCK_SIZE),
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readw(host->ioaddr + SDHCI_BLOCK_COUNT));
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printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
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readl(host->ioaddr + SDHCI_ARGUMENT),
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readw(host->ioaddr + SDHCI_TRANSFER_MODE));
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printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
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readl(host->ioaddr + SDHCI_PRESENT_STATE),
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readb(host->ioaddr + SDHCI_HOST_CONTROL));
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printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
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readb(host->ioaddr + SDHCI_POWER_CONTROL),
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readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
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printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
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readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL),
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readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
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printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
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readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
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readl(host->ioaddr + SDHCI_INT_STATUS));
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printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
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readl(host->ioaddr + SDHCI_INT_ENABLE),
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readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
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printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
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readw(host->ioaddr + SDHCI_ACMD12_ERR),
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readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
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printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
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readl(host->ioaddr + SDHCI_CAPABILITIES),
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readl(host->ioaddr + SDHCI_MAX_CURRENT));
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printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
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}
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/*****************************************************************************\
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* *
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* Low level functions *
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* *
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\*****************************************************************************/
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static void sdhci_reset(struct sdhci_host *host, u8 mask)
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{
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unsigned long timeout;
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if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
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if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
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SDHCI_CARD_PRESENT))
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return;
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}
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writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
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if (mask & SDHCI_RESET_ALL)
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host->clock = 0;
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/* Wait max 100 ms */
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timeout = 100;
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/* hw clears the bit when it's done */
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while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
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if (timeout == 0) {
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printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
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mmc_hostname(host->mmc), (int)mask);
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sdhci_dumpregs(host);
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return;
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}
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timeout--;
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mdelay(1);
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}
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}
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static void sdhci_init(struct sdhci_host *host)
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{
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u32 intmask;
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sdhci_reset(host, SDHCI_RESET_ALL);
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intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
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SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
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SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
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SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
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SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
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SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
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writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
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writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
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}
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static void sdhci_activate_led(struct sdhci_host *host)
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{
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u8 ctrl;
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ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
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ctrl |= SDHCI_CTRL_LED;
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writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
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}
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static void sdhci_deactivate_led(struct sdhci_host *host)
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{
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u8 ctrl;
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ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
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ctrl &= ~SDHCI_CTRL_LED;
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writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
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}
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#ifdef CONFIG_LEDS_CLASS
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static void sdhci_led_control(struct led_classdev *led,
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enum led_brightness brightness)
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{
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struct sdhci_host *host = container_of(led, struct sdhci_host, led);
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unsigned long flags;
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spin_lock_irqsave(&host->lock, flags);
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if (brightness == LED_OFF)
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sdhci_deactivate_led(host);
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else
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sdhci_activate_led(host);
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spin_unlock_irqrestore(&host->lock, flags);
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}
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#endif
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/*****************************************************************************\
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* *
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* Core functions *
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* *
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\*****************************************************************************/
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static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
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{
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return sg_virt(host->cur_sg);
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}
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static inline int sdhci_next_sg(struct sdhci_host* host)
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{
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/*
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* Skip to next SG entry.
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*/
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host->cur_sg++;
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host->num_sg--;
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/*
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* Any entries left?
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*/
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if (host->num_sg > 0) {
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host->offset = 0;
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host->remain = host->cur_sg->length;
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}
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return host->num_sg;
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}
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static void sdhci_read_block_pio(struct sdhci_host *host)
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{
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int blksize, chunk_remain;
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u32 data;
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char *buffer;
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int size;
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DBG("PIO reading\n");
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blksize = host->data->blksz;
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chunk_remain = 0;
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data = 0;
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buffer = sdhci_sg_to_buffer(host) + host->offset;
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while (blksize) {
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if (chunk_remain == 0) {
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data = readl(host->ioaddr + SDHCI_BUFFER);
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chunk_remain = min(blksize, 4);
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}
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size = min(host->remain, chunk_remain);
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chunk_remain -= size;
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blksize -= size;
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host->offset += size;
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host->remain -= size;
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while (size) {
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*buffer = data & 0xFF;
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buffer++;
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data >>= 8;
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size--;
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}
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if (host->remain == 0) {
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if (sdhci_next_sg(host) == 0) {
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BUG_ON(blksize != 0);
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return;
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}
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buffer = sdhci_sg_to_buffer(host);
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}
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}
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}
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static void sdhci_write_block_pio(struct sdhci_host *host)
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{
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int blksize, chunk_remain;
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u32 data;
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char *buffer;
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int bytes, size;
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DBG("PIO writing\n");
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blksize = host->data->blksz;
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chunk_remain = 4;
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data = 0;
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bytes = 0;
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buffer = sdhci_sg_to_buffer(host) + host->offset;
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while (blksize) {
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size = min(host->remain, chunk_remain);
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chunk_remain -= size;
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blksize -= size;
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host->offset += size;
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host->remain -= size;
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while (size) {
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data >>= 8;
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data |= (u32)*buffer << 24;
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buffer++;
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size--;
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}
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if (chunk_remain == 0) {
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writel(data, host->ioaddr + SDHCI_BUFFER);
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chunk_remain = min(blksize, 4);
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}
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if (host->remain == 0) {
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if (sdhci_next_sg(host) == 0) {
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BUG_ON(blksize != 0);
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return;
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}
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buffer = sdhci_sg_to_buffer(host);
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}
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}
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}
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static void sdhci_transfer_pio(struct sdhci_host *host)
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{
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u32 mask;
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BUG_ON(!host->data);
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if (host->num_sg == 0)
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return;
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if (host->data->flags & MMC_DATA_READ)
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mask = SDHCI_DATA_AVAILABLE;
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else
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mask = SDHCI_SPACE_AVAILABLE;
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while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
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if (host->data->flags & MMC_DATA_READ)
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sdhci_read_block_pio(host);
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else
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sdhci_write_block_pio(host);
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if (host->num_sg == 0)
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break;
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}
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DBG("PIO transfer complete.\n");
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}
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static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
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{
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u8 count;
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unsigned target_timeout, current_timeout;
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WARN_ON(host->data);
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if (data == NULL)
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return;
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/* Sanity checks */
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BUG_ON(data->blksz * data->blocks > 524288);
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BUG_ON(data->blksz > host->mmc->max_blk_size);
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BUG_ON(data->blocks > 65535);
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host->data = data;
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host->data_early = 0;
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/* timeout in us */
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target_timeout = data->timeout_ns / 1000 +
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data->timeout_clks / host->clock;
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/*
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* Figure out needed cycles.
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* We do this in steps in order to fit inside a 32 bit int.
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* The first step is the minimum timeout, which will have a
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* minimum resolution of 6 bits:
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* (1) 2^13*1000 > 2^22,
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* (2) host->timeout_clk < 2^16
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* =>
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* (1) / (2) > 2^6
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*/
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count = 0;
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current_timeout = (1 << 13) * 1000 / host->timeout_clk;
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while (current_timeout < target_timeout) {
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count++;
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current_timeout <<= 1;
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if (count >= 0xF)
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break;
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}
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/*
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* Compensate for an off-by-one error in the CaFe hardware; otherwise,
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* a too-small count gives us interrupt timeouts.
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*/
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if ((host->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL))
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count++;
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if (count >= 0xF) {
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printk(KERN_WARNING "%s: Too large timeout requested!\n",
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mmc_hostname(host->mmc));
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count = 0xE;
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}
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writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
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if (host->flags & SDHCI_USE_DMA)
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host->flags |= SDHCI_REQ_USE_DMA;
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if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
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(host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
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((data->blksz * data->blocks) & 0x3))) {
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DBG("Reverting to PIO because of transfer size (%d)\n",
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data->blksz * data->blocks);
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host->flags &= ~SDHCI_REQ_USE_DMA;
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}
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/*
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* The assumption here being that alignment is the same after
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* translation to device address space.
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*/
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if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
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(host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
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(data->sg->offset & 0x3))) {
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DBG("Reverting to PIO because of bad alignment\n");
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host->flags &= ~SDHCI_REQ_USE_DMA;
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}
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if (host->flags & SDHCI_REQ_USE_DMA) {
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int count;
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count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
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(data->flags & MMC_DATA_READ) ?
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DMA_FROM_DEVICE : DMA_TO_DEVICE);
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WARN_ON(count != 1);
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writel(sg_dma_address(data->sg),
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host->ioaddr + SDHCI_DMA_ADDRESS);
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} else {
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host->cur_sg = data->sg;
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host->num_sg = data->sg_len;
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host->offset = 0;
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host->remain = host->cur_sg->length;
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}
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/* We do not handle DMA boundaries, so set it to max (512 KiB) */
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writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
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host->ioaddr + SDHCI_BLOCK_SIZE);
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writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
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}
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static void sdhci_set_transfer_mode(struct sdhci_host *host,
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struct mmc_data *data)
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{
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u16 mode;
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if (data == NULL)
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return;
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WARN_ON(!host->data);
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mode = SDHCI_TRNS_BLK_CNT_EN;
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if (data->blocks > 1)
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mode |= SDHCI_TRNS_MULTI;
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if (data->flags & MMC_DATA_READ)
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mode |= SDHCI_TRNS_READ;
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if (host->flags & SDHCI_REQ_USE_DMA)
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mode |= SDHCI_TRNS_DMA;
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writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
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}
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static void sdhci_finish_data(struct sdhci_host *host)
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{
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struct mmc_data *data;
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BUG_ON(!host->data);
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data = host->data;
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host->data = NULL;
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if (host->flags & SDHCI_REQ_USE_DMA) {
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dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
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(data->flags & MMC_DATA_READ) ?
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DMA_FROM_DEVICE : DMA_TO_DEVICE);
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}
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/*
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* The specification states that the block count register must
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* be updated, but it does not specify at what point in the
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* data flow. That makes the register entirely useless to read
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* back so we have to assume that nothing made it to the card
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* in the event of an error.
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*/
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if (data->error)
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data->bytes_xfered = 0;
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else
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data->bytes_xfered = data->blksz * data->blocks;
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if (data->stop) {
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/*
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* The controller needs a reset of internal state machines
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* upon error conditions.
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*/
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if (data->error) {
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sdhci_reset(host, SDHCI_RESET_CMD);
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sdhci_reset(host, SDHCI_RESET_DATA);
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}
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sdhci_send_command(host, data->stop);
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} else
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tasklet_schedule(&host->finish_tasklet);
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}
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static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
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{
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int flags;
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u32 mask;
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unsigned long timeout;
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WARN_ON(host->cmd);
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/* Wait max 10 ms */
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timeout = 10;
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mask = SDHCI_CMD_INHIBIT;
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if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
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mask |= SDHCI_DATA_INHIBIT;
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/* We shouldn't wait for data inihibit for stop commands, even
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though they might use busy signaling */
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if (host->mrq->data && (cmd == host->mrq->data->stop))
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mask &= ~SDHCI_DATA_INHIBIT;
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while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
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if (timeout == 0) {
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printk(KERN_ERR "%s: Controller never released "
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"inhibit bit(s).\n", mmc_hostname(host->mmc));
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sdhci_dumpregs(host);
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cmd->error = -EIO;
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tasklet_schedule(&host->finish_tasklet);
|
|
return;
|
|
}
|
|
timeout--;
|
|
mdelay(1);
|
|
}
|
|
|
|
mod_timer(&host->timer, jiffies + 10 * HZ);
|
|
|
|
host->cmd = cmd;
|
|
|
|
sdhci_prepare_data(host, cmd->data);
|
|
|
|
writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
|
|
|
|
sdhci_set_transfer_mode(host, cmd->data);
|
|
|
|
if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
|
|
printk(KERN_ERR "%s: Unsupported response type!\n",
|
|
mmc_hostname(host->mmc));
|
|
cmd->error = -EINVAL;
|
|
tasklet_schedule(&host->finish_tasklet);
|
|
return;
|
|
}
|
|
|
|
if (!(cmd->flags & MMC_RSP_PRESENT))
|
|
flags = SDHCI_CMD_RESP_NONE;
|
|
else if (cmd->flags & MMC_RSP_136)
|
|
flags = SDHCI_CMD_RESP_LONG;
|
|
else if (cmd->flags & MMC_RSP_BUSY)
|
|
flags = SDHCI_CMD_RESP_SHORT_BUSY;
|
|
else
|
|
flags = SDHCI_CMD_RESP_SHORT;
|
|
|
|
if (cmd->flags & MMC_RSP_CRC)
|
|
flags |= SDHCI_CMD_CRC;
|
|
if (cmd->flags & MMC_RSP_OPCODE)
|
|
flags |= SDHCI_CMD_INDEX;
|
|
if (cmd->data)
|
|
flags |= SDHCI_CMD_DATA;
|
|
|
|
writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
|
|
host->ioaddr + SDHCI_COMMAND);
|
|
}
|
|
|
|
static void sdhci_finish_command(struct sdhci_host *host)
|
|
{
|
|
int i;
|
|
|
|
BUG_ON(host->cmd == NULL);
|
|
|
|
if (host->cmd->flags & MMC_RSP_PRESENT) {
|
|
if (host->cmd->flags & MMC_RSP_136) {
|
|
/* CRC is stripped so we need to do some shifting. */
|
|
for (i = 0;i < 4;i++) {
|
|
host->cmd->resp[i] = readl(host->ioaddr +
|
|
SDHCI_RESPONSE + (3-i)*4) << 8;
|
|
if (i != 3)
|
|
host->cmd->resp[i] |=
|
|
readb(host->ioaddr +
|
|
SDHCI_RESPONSE + (3-i)*4-1);
|
|
}
|
|
} else {
|
|
host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
|
|
}
|
|
}
|
|
|
|
host->cmd->error = 0;
|
|
|
|
if (host->data && host->data_early)
|
|
sdhci_finish_data(host);
|
|
|
|
if (!host->cmd->data)
|
|
tasklet_schedule(&host->finish_tasklet);
|
|
|
|
host->cmd = NULL;
|
|
}
|
|
|
|
static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
|
|
{
|
|
int div;
|
|
u16 clk;
|
|
unsigned long timeout;
|
|
|
|
if (clock == host->clock)
|
|
return;
|
|
|
|
writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
|
|
|
|
if (clock == 0)
|
|
goto out;
|
|
|
|
for (div = 1;div < 256;div *= 2) {
|
|
if ((host->max_clk / div) <= clock)
|
|
break;
|
|
}
|
|
div >>= 1;
|
|
|
|
clk = div << SDHCI_DIVIDER_SHIFT;
|
|
clk |= SDHCI_CLOCK_INT_EN;
|
|
writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
|
|
|
|
/* Wait max 10 ms */
|
|
timeout = 10;
|
|
while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
|
|
& SDHCI_CLOCK_INT_STABLE)) {
|
|
if (timeout == 0) {
|
|
printk(KERN_ERR "%s: Internal clock never "
|
|
"stabilised.\n", mmc_hostname(host->mmc));
|
|
sdhci_dumpregs(host);
|
|
return;
|
|
}
|
|
timeout--;
|
|
mdelay(1);
|
|
}
|
|
|
|
clk |= SDHCI_CLOCK_CARD_EN;
|
|
writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
|
|
|
|
out:
|
|
host->clock = clock;
|
|
}
|
|
|
|
static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
|
|
{
|
|
u8 pwr;
|
|
|
|
if (host->power == power)
|
|
return;
|
|
|
|
if (power == (unsigned short)-1) {
|
|
writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* Spec says that we should clear the power reg before setting
|
|
* a new value. Some controllers don't seem to like this though.
|
|
*/
|
|
if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
|
|
writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
|
|
|
|
pwr = SDHCI_POWER_ON;
|
|
|
|
switch (1 << power) {
|
|
case MMC_VDD_165_195:
|
|
pwr |= SDHCI_POWER_180;
|
|
break;
|
|
case MMC_VDD_29_30:
|
|
case MMC_VDD_30_31:
|
|
pwr |= SDHCI_POWER_300;
|
|
break;
|
|
case MMC_VDD_32_33:
|
|
case MMC_VDD_33_34:
|
|
pwr |= SDHCI_POWER_330;
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
|
|
/*
|
|
* At least the CaFe chip gets confused if we set the voltage
|
|
* and set turn on power at the same time, so set the voltage first.
|
|
*/
|
|
if ((host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER))
|
|
writeb(pwr & ~SDHCI_POWER_ON,
|
|
host->ioaddr + SDHCI_POWER_CONTROL);
|
|
|
|
writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
|
|
|
|
out:
|
|
host->power = power;
|
|
}
|
|
|
|
/*****************************************************************************\
|
|
* *
|
|
* MMC callbacks *
|
|
* *
|
|
\*****************************************************************************/
|
|
|
|
static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
|
{
|
|
struct sdhci_host *host;
|
|
unsigned long flags;
|
|
|
|
host = mmc_priv(mmc);
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
WARN_ON(host->mrq != NULL);
|
|
|
|
#ifndef CONFIG_LEDS_CLASS
|
|
sdhci_activate_led(host);
|
|
#endif
|
|
|
|
host->mrq = mrq;
|
|
|
|
if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
|
|
host->mrq->cmd->error = -ENOMEDIUM;
|
|
tasklet_schedule(&host->finish_tasklet);
|
|
} else
|
|
sdhci_send_command(host, mrq->cmd);
|
|
|
|
mmiowb();
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
}
|
|
|
|
static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
{
|
|
struct sdhci_host *host;
|
|
unsigned long flags;
|
|
u8 ctrl;
|
|
|
|
host = mmc_priv(mmc);
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
/*
|
|
* Reset the chip on each power off.
|
|
* Should clear out any weird states.
|
|
*/
|
|
if (ios->power_mode == MMC_POWER_OFF) {
|
|
writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
|
|
sdhci_init(host);
|
|
}
|
|
|
|
sdhci_set_clock(host, ios->clock);
|
|
|
|
if (ios->power_mode == MMC_POWER_OFF)
|
|
sdhci_set_power(host, -1);
|
|
else
|
|
sdhci_set_power(host, ios->vdd);
|
|
|
|
ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
|
|
|
|
if (ios->bus_width == MMC_BUS_WIDTH_4)
|
|
ctrl |= SDHCI_CTRL_4BITBUS;
|
|
else
|
|
ctrl &= ~SDHCI_CTRL_4BITBUS;
|
|
|
|
if (ios->timing == MMC_TIMING_SD_HS)
|
|
ctrl |= SDHCI_CTRL_HISPD;
|
|
else
|
|
ctrl &= ~SDHCI_CTRL_HISPD;
|
|
|
|
writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
|
|
|
|
/*
|
|
* Some (ENE) controllers go apeshit on some ios operation,
|
|
* signalling timeout and CRC errors even on CMD0. Resetting
|
|
* it on each ios seems to solve the problem.
|
|
*/
|
|
if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
|
|
sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
|
|
|
|
mmiowb();
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
}
|
|
|
|
static int sdhci_get_ro(struct mmc_host *mmc)
|
|
{
|
|
struct sdhci_host *host;
|
|
unsigned long flags;
|
|
int present;
|
|
|
|
host = mmc_priv(mmc);
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
return !(present & SDHCI_WRITE_PROTECT);
|
|
}
|
|
|
|
static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
|
|
{
|
|
struct sdhci_host *host;
|
|
unsigned long flags;
|
|
u32 ier;
|
|
|
|
host = mmc_priv(mmc);
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
ier = readl(host->ioaddr + SDHCI_INT_ENABLE);
|
|
|
|
ier &= ~SDHCI_INT_CARD_INT;
|
|
if (enable)
|
|
ier |= SDHCI_INT_CARD_INT;
|
|
|
|
writel(ier, host->ioaddr + SDHCI_INT_ENABLE);
|
|
writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
|
|
|
|
mmiowb();
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
}
|
|
|
|
static const struct mmc_host_ops sdhci_ops = {
|
|
.request = sdhci_request,
|
|
.set_ios = sdhci_set_ios,
|
|
.get_ro = sdhci_get_ro,
|
|
.enable_sdio_irq = sdhci_enable_sdio_irq,
|
|
};
|
|
|
|
/*****************************************************************************\
|
|
* *
|
|
* Tasklets *
|
|
* *
|
|
\*****************************************************************************/
|
|
|
|
static void sdhci_tasklet_card(unsigned long param)
|
|
{
|
|
struct sdhci_host *host;
|
|
unsigned long flags;
|
|
|
|
host = (struct sdhci_host*)param;
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
|
|
if (host->mrq) {
|
|
printk(KERN_ERR "%s: Card removed during transfer!\n",
|
|
mmc_hostname(host->mmc));
|
|
printk(KERN_ERR "%s: Resetting controller.\n",
|
|
mmc_hostname(host->mmc));
|
|
|
|
sdhci_reset(host, SDHCI_RESET_CMD);
|
|
sdhci_reset(host, SDHCI_RESET_DATA);
|
|
|
|
host->mrq->cmd->error = -ENOMEDIUM;
|
|
tasklet_schedule(&host->finish_tasklet);
|
|
}
|
|
}
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
mmc_detect_change(host->mmc, msecs_to_jiffies(500));
|
|
}
|
|
|
|
static void sdhci_tasklet_finish(unsigned long param)
|
|
{
|
|
struct sdhci_host *host;
|
|
unsigned long flags;
|
|
struct mmc_request *mrq;
|
|
|
|
host = (struct sdhci_host*)param;
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
del_timer(&host->timer);
|
|
|
|
mrq = host->mrq;
|
|
|
|
/*
|
|
* The controller needs a reset of internal state machines
|
|
* upon error conditions.
|
|
*/
|
|
if (mrq->cmd->error ||
|
|
(mrq->data && (mrq->data->error ||
|
|
(mrq->data->stop && mrq->data->stop->error))) ||
|
|
(host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
|
|
|
|
/* Some controllers need this kick or reset won't work here */
|
|
if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
|
|
unsigned int clock;
|
|
|
|
/* This is to force an update */
|
|
clock = host->clock;
|
|
host->clock = 0;
|
|
sdhci_set_clock(host, clock);
|
|
}
|
|
|
|
/* Spec says we should do both at the same time, but Ricoh
|
|
controllers do not like that. */
|
|
sdhci_reset(host, SDHCI_RESET_CMD);
|
|
sdhci_reset(host, SDHCI_RESET_DATA);
|
|
}
|
|
|
|
host->mrq = NULL;
|
|
host->cmd = NULL;
|
|
host->data = NULL;
|
|
|
|
#ifndef CONFIG_LEDS_CLASS
|
|
sdhci_deactivate_led(host);
|
|
#endif
|
|
|
|
mmiowb();
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
mmc_request_done(host->mmc, mrq);
|
|
}
|
|
|
|
static void sdhci_timeout_timer(unsigned long data)
|
|
{
|
|
struct sdhci_host *host;
|
|
unsigned long flags;
|
|
|
|
host = (struct sdhci_host*)data;
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
if (host->mrq) {
|
|
printk(KERN_ERR "%s: Timeout waiting for hardware "
|
|
"interrupt.\n", mmc_hostname(host->mmc));
|
|
sdhci_dumpregs(host);
|
|
|
|
if (host->data) {
|
|
host->data->error = -ETIMEDOUT;
|
|
sdhci_finish_data(host);
|
|
} else {
|
|
if (host->cmd)
|
|
host->cmd->error = -ETIMEDOUT;
|
|
else
|
|
host->mrq->cmd->error = -ETIMEDOUT;
|
|
|
|
tasklet_schedule(&host->finish_tasklet);
|
|
}
|
|
}
|
|
|
|
mmiowb();
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
}
|
|
|
|
/*****************************************************************************\
|
|
* *
|
|
* Interrupt handling *
|
|
* *
|
|
\*****************************************************************************/
|
|
|
|
static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
|
|
{
|
|
BUG_ON(intmask == 0);
|
|
|
|
if (!host->cmd) {
|
|
printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
|
|
"though no command operation was in progress.\n",
|
|
mmc_hostname(host->mmc), (unsigned)intmask);
|
|
sdhci_dumpregs(host);
|
|
return;
|
|
}
|
|
|
|
if (intmask & SDHCI_INT_TIMEOUT)
|
|
host->cmd->error = -ETIMEDOUT;
|
|
else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
|
|
SDHCI_INT_INDEX))
|
|
host->cmd->error = -EILSEQ;
|
|
|
|
if (host->cmd->error)
|
|
tasklet_schedule(&host->finish_tasklet);
|
|
else if (intmask & SDHCI_INT_RESPONSE)
|
|
sdhci_finish_command(host);
|
|
}
|
|
|
|
static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
|
|
{
|
|
BUG_ON(intmask == 0);
|
|
|
|
if (!host->data) {
|
|
/*
|
|
* A data end interrupt is sent together with the response
|
|
* for the stop command.
|
|
*/
|
|
if (intmask & SDHCI_INT_DATA_END)
|
|
return;
|
|
|
|
printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
|
|
"though no data operation was in progress.\n",
|
|
mmc_hostname(host->mmc), (unsigned)intmask);
|
|
sdhci_dumpregs(host);
|
|
|
|
return;
|
|
}
|
|
|
|
if (intmask & SDHCI_INT_DATA_TIMEOUT)
|
|
host->data->error = -ETIMEDOUT;
|
|
else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
|
|
host->data->error = -EILSEQ;
|
|
|
|
if (host->data->error)
|
|
sdhci_finish_data(host);
|
|
else {
|
|
if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
|
|
sdhci_transfer_pio(host);
|
|
|
|
/*
|
|
* We currently don't do anything fancy with DMA
|
|
* boundaries, but as we can't disable the feature
|
|
* we need to at least restart the transfer.
|
|
*/
|
|
if (intmask & SDHCI_INT_DMA_END)
|
|
writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
|
|
host->ioaddr + SDHCI_DMA_ADDRESS);
|
|
|
|
if (intmask & SDHCI_INT_DATA_END) {
|
|
if (host->cmd) {
|
|
/*
|
|
* Data managed to finish before the
|
|
* command completed. Make sure we do
|
|
* things in the proper order.
|
|
*/
|
|
host->data_early = 1;
|
|
} else {
|
|
sdhci_finish_data(host);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
static irqreturn_t sdhci_irq(int irq, void *dev_id)
|
|
{
|
|
irqreturn_t result;
|
|
struct sdhci_host* host = dev_id;
|
|
u32 intmask;
|
|
int cardint = 0;
|
|
|
|
spin_lock(&host->lock);
|
|
|
|
intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
|
|
|
|
if (!intmask || intmask == 0xffffffff) {
|
|
result = IRQ_NONE;
|
|
goto out;
|
|
}
|
|
|
|
DBG("*** %s got interrupt: 0x%08x\n",
|
|
mmc_hostname(host->mmc), intmask);
|
|
|
|
if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
|
|
writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
|
|
host->ioaddr + SDHCI_INT_STATUS);
|
|
tasklet_schedule(&host->card_tasklet);
|
|
}
|
|
|
|
intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
|
|
|
|
if (intmask & SDHCI_INT_CMD_MASK) {
|
|
writel(intmask & SDHCI_INT_CMD_MASK,
|
|
host->ioaddr + SDHCI_INT_STATUS);
|
|
sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
|
|
}
|
|
|
|
if (intmask & SDHCI_INT_DATA_MASK) {
|
|
writel(intmask & SDHCI_INT_DATA_MASK,
|
|
host->ioaddr + SDHCI_INT_STATUS);
|
|
sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
|
|
}
|
|
|
|
intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
|
|
|
|
intmask &= ~SDHCI_INT_ERROR;
|
|
|
|
if (intmask & SDHCI_INT_BUS_POWER) {
|
|
printk(KERN_ERR "%s: Card is consuming too much power!\n",
|
|
mmc_hostname(host->mmc));
|
|
writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
|
|
}
|
|
|
|
intmask &= ~SDHCI_INT_BUS_POWER;
|
|
|
|
if (intmask & SDHCI_INT_CARD_INT)
|
|
cardint = 1;
|
|
|
|
intmask &= ~SDHCI_INT_CARD_INT;
|
|
|
|
if (intmask) {
|
|
printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
|
|
mmc_hostname(host->mmc), intmask);
|
|
sdhci_dumpregs(host);
|
|
|
|
writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
|
|
}
|
|
|
|
result = IRQ_HANDLED;
|
|
|
|
mmiowb();
|
|
out:
|
|
spin_unlock(&host->lock);
|
|
|
|
/*
|
|
* We have to delay this as it calls back into the driver.
|
|
*/
|
|
if (cardint)
|
|
mmc_signal_sdio_irq(host->mmc);
|
|
|
|
return result;
|
|
}
|
|
|
|
/*****************************************************************************\
|
|
* *
|
|
* Suspend/resume *
|
|
* *
|
|
\*****************************************************************************/
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
|
|
{
|
|
int ret;
|
|
|
|
ret = mmc_suspend_host(host->mmc, state);
|
|
if (ret)
|
|
return ret;
|
|
|
|
free_irq(host->irq, host);
|
|
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(sdhci_suspend_host);
|
|
|
|
int sdhci_resume_host(struct sdhci_host *host)
|
|
{
|
|
int ret;
|
|
|
|
if (host->flags & SDHCI_USE_DMA) {
|
|
if (host->ops->enable_dma)
|
|
host->ops->enable_dma(host);
|
|
}
|
|
|
|
ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
|
|
mmc_hostname(host->mmc), host);
|
|
if (ret)
|
|
return ret;
|
|
|
|
sdhci_init(host);
|
|
mmiowb();
|
|
|
|
ret = mmc_resume_host(host->mmc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(sdhci_resume_host);
|
|
|
|
#endif /* CONFIG_PM */
|
|
|
|
/*****************************************************************************\
|
|
* *
|
|
* Device allocation/registration *
|
|
* *
|
|
\*****************************************************************************/
|
|
|
|
struct sdhci_host *sdhci_alloc_host(struct device *dev,
|
|
size_t priv_size)
|
|
{
|
|
struct mmc_host *mmc;
|
|
struct sdhci_host *host;
|
|
|
|
WARN_ON(dev == NULL);
|
|
|
|
mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
|
|
if (!mmc)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
host = mmc_priv(mmc);
|
|
host->mmc = mmc;
|
|
|
|
return host;
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(sdhci_alloc_host);
|
|
|
|
int sdhci_add_host(struct sdhci_host *host)
|
|
{
|
|
struct mmc_host *mmc;
|
|
unsigned int caps;
|
|
unsigned int version;
|
|
int ret;
|
|
|
|
WARN_ON(host == NULL);
|
|
if (host == NULL)
|
|
return -EINVAL;
|
|
|
|
mmc = host->mmc;
|
|
|
|
if (debug_quirks)
|
|
host->quirks = debug_quirks;
|
|
|
|
sdhci_reset(host, SDHCI_RESET_ALL);
|
|
|
|
version = readw(host->ioaddr + SDHCI_HOST_VERSION);
|
|
version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
|
|
if (version > 1) {
|
|
printk(KERN_ERR "%s: Unknown controller version (%d). "
|
|
"You may experience problems.\n", mmc_hostname(mmc),
|
|
version);
|
|
}
|
|
|
|
caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
|
|
|
|
if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
|
|
host->flags |= SDHCI_USE_DMA;
|
|
else if (!(caps & SDHCI_CAN_DO_DMA))
|
|
DBG("Controller doesn't have DMA capability\n");
|
|
else
|
|
host->flags |= SDHCI_USE_DMA;
|
|
|
|
if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
|
|
(host->flags & SDHCI_USE_DMA)) {
|
|
DBG("Disabling DMA as it is marked broken\n");
|
|
host->flags &= ~SDHCI_USE_DMA;
|
|
}
|
|
|
|
if (host->flags & SDHCI_USE_DMA) {
|
|
if (host->ops->enable_dma) {
|
|
if (host->ops->enable_dma(host)) {
|
|
printk(KERN_WARNING "%s: No suitable DMA "
|
|
"available. Falling back to PIO.\n",
|
|
mmc_hostname(mmc));
|
|
host->flags &= ~SDHCI_USE_DMA;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* XXX: Hack to get MMC layer to avoid highmem */
|
|
if (!(host->flags & SDHCI_USE_DMA))
|
|
mmc_dev(host->mmc)->dma_mask = 0;
|
|
|
|
host->max_clk =
|
|
(caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
|
|
if (host->max_clk == 0) {
|
|
printk(KERN_ERR "%s: Hardware doesn't specify base clock "
|
|
"frequency.\n", mmc_hostname(mmc));
|
|
return -ENODEV;
|
|
}
|
|
host->max_clk *= 1000000;
|
|
|
|
host->timeout_clk =
|
|
(caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
|
|
if (host->timeout_clk == 0) {
|
|
printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
|
|
"frequency.\n", mmc_hostname(mmc));
|
|
return -ENODEV;
|
|
}
|
|
if (caps & SDHCI_TIMEOUT_CLK_UNIT)
|
|
host->timeout_clk *= 1000;
|
|
|
|
/*
|
|
* Set host parameters.
|
|
*/
|
|
mmc->ops = &sdhci_ops;
|
|
mmc->f_min = host->max_clk / 256;
|
|
mmc->f_max = host->max_clk;
|
|
mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
|
|
|
|
if (caps & SDHCI_CAN_DO_HISPD)
|
|
mmc->caps |= MMC_CAP_SD_HIGHSPEED;
|
|
|
|
mmc->ocr_avail = 0;
|
|
if (caps & SDHCI_CAN_VDD_330)
|
|
mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
|
|
if (caps & SDHCI_CAN_VDD_300)
|
|
mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
|
|
if (caps & SDHCI_CAN_VDD_180)
|
|
mmc->ocr_avail |= MMC_VDD_165_195;
|
|
|
|
if (mmc->ocr_avail == 0) {
|
|
printk(KERN_ERR "%s: Hardware doesn't report any "
|
|
"support voltages.\n", mmc_hostname(mmc));
|
|
return -ENODEV;
|
|
}
|
|
|
|
spin_lock_init(&host->lock);
|
|
|
|
/*
|
|
* Maximum number of segments. Hardware cannot do scatter lists.
|
|
*/
|
|
if (host->flags & SDHCI_USE_DMA)
|
|
mmc->max_hw_segs = 1;
|
|
else
|
|
mmc->max_hw_segs = 16;
|
|
mmc->max_phys_segs = 16;
|
|
|
|
/*
|
|
* Maximum number of sectors in one transfer. Limited by DMA boundary
|
|
* size (512KiB).
|
|
*/
|
|
mmc->max_req_size = 524288;
|
|
|
|
/*
|
|
* Maximum segment size. Could be one segment with the maximum number
|
|
* of bytes.
|
|
*/
|
|
mmc->max_seg_size = mmc->max_req_size;
|
|
|
|
/*
|
|
* Maximum block size. This varies from controller to controller and
|
|
* is specified in the capabilities register.
|
|
*/
|
|
mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
|
|
if (mmc->max_blk_size >= 3) {
|
|
printk(KERN_WARNING "%s: Invalid maximum block size, "
|
|
"assuming 512 bytes\n", mmc_hostname(mmc));
|
|
mmc->max_blk_size = 512;
|
|
} else
|
|
mmc->max_blk_size = 512 << mmc->max_blk_size;
|
|
|
|
/*
|
|
* Maximum block count.
|
|
*/
|
|
mmc->max_blk_count = 65535;
|
|
|
|
/*
|
|
* Init tasklets.
|
|
*/
|
|
tasklet_init(&host->card_tasklet,
|
|
sdhci_tasklet_card, (unsigned long)host);
|
|
tasklet_init(&host->finish_tasklet,
|
|
sdhci_tasklet_finish, (unsigned long)host);
|
|
|
|
setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
|
|
|
|
ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
|
|
mmc_hostname(mmc), host);
|
|
if (ret)
|
|
goto untasklet;
|
|
|
|
sdhci_init(host);
|
|
|
|
#ifdef CONFIG_MMC_DEBUG
|
|
sdhci_dumpregs(host);
|
|
#endif
|
|
|
|
#ifdef CONFIG_LEDS_CLASS
|
|
host->led.name = mmc_hostname(mmc);
|
|
host->led.brightness = LED_OFF;
|
|
host->led.default_trigger = mmc_hostname(mmc);
|
|
host->led.brightness_set = sdhci_led_control;
|
|
|
|
ret = led_classdev_register(mmc_dev(mmc), &host->led);
|
|
if (ret)
|
|
goto reset;
|
|
#endif
|
|
|
|
mmiowb();
|
|
|
|
mmc_add_host(mmc);
|
|
|
|
printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
|
|
mmc_hostname(mmc), host->hw_name, mmc_dev(mmc)->bus_id,
|
|
(host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
|
|
|
|
return 0;
|
|
|
|
#ifdef CONFIG_LEDS_CLASS
|
|
reset:
|
|
sdhci_reset(host, SDHCI_RESET_ALL);
|
|
free_irq(host->irq, host);
|
|
#endif
|
|
untasklet:
|
|
tasklet_kill(&host->card_tasklet);
|
|
tasklet_kill(&host->finish_tasklet);
|
|
|
|
return ret;
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(sdhci_add_host);
|
|
|
|
void sdhci_remove_host(struct sdhci_host *host)
|
|
{
|
|
mmc_remove_host(host->mmc);
|
|
|
|
#ifdef CONFIG_LEDS_CLASS
|
|
led_classdev_unregister(&host->led);
|
|
#endif
|
|
|
|
sdhci_reset(host, SDHCI_RESET_ALL);
|
|
|
|
free_irq(host->irq, host);
|
|
|
|
del_timer_sync(&host->timer);
|
|
|
|
tasklet_kill(&host->card_tasklet);
|
|
tasklet_kill(&host->finish_tasklet);
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(sdhci_remove_host);
|
|
|
|
void sdhci_free_host(struct sdhci_host *host)
|
|
{
|
|
mmc_free_host(host->mmc);
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(sdhci_free_host);
|
|
|
|
/*****************************************************************************\
|
|
* *
|
|
* Driver init/exit *
|
|
* *
|
|
\*****************************************************************************/
|
|
|
|
static int __init sdhci_drv_init(void)
|
|
{
|
|
printk(KERN_INFO DRIVER_NAME
|
|
": Secure Digital Host Controller Interface driver\n");
|
|
printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __exit sdhci_drv_exit(void)
|
|
{
|
|
}
|
|
|
|
module_init(sdhci_drv_init);
|
|
module_exit(sdhci_drv_exit);
|
|
|
|
module_param(debug_quirks, uint, 0444);
|
|
|
|
MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
|
|
MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
|