forked from Minki/linux
cd4a05f9df
This allows us to have more mapping functions for more than one i.MX architecture in the kernel. As this is the earliest board specific hook we have, also use it to set the cpu type. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
557 lines
14 KiB
C
557 lines
14 KiB
C
/*
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/serial_8250.h>
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#include <linux/gpio.h>
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#include <linux/i2c.h>
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#include <linux/irq.h>
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#include <mach/hardware.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <asm/memory.h>
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#include <asm/mach/map.h>
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#include <mach/common.h>
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#include <mach/board-mx31ads.h>
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#include <mach/imx-uart.h>
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#include <mach/iomux-mx3.h>
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#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
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#include <linux/mfd/wm8350/audio.h>
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#include <linux/mfd/wm8350/core.h>
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#include <linux/mfd/wm8350/pmic.h>
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#endif
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#include "devices.h"
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/*!
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* @file mx31ads.c
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*
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* @brief This file contains the board-specific initialization routines.
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*
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* @ingroup System
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*/
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#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
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/*!
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* The serial port definition structure.
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*/
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static struct plat_serial8250_port serial_platform_data[] = {
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{
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.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
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.mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTA),
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.irq = EXPIO_INT_XUART_INTA,
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.uartclk = 14745600,
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.regshift = 0,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
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}, {
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.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
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.mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTB),
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.irq = EXPIO_INT_XUART_INTB,
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.uartclk = 14745600,
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.regshift = 0,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
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},
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{},
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};
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static struct platform_device serial_device = {
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.name = "serial8250",
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.id = 0,
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.dev = {
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.platform_data = serial_platform_data,
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},
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};
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static int __init mxc_init_extuart(void)
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{
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return platform_device_register(&serial_device);
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}
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#else
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static inline int mxc_init_extuart(void)
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{
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return 0;
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}
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#endif
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#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
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static struct imxuart_platform_data uart_pdata = {
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.flags = IMXUART_HAVE_RTSCTS,
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};
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static unsigned int uart_pins[] = {
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MX31_PIN_CTS1__CTS1,
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MX31_PIN_RTS1__RTS1,
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MX31_PIN_TXD1__TXD1,
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MX31_PIN_RXD1__RXD1
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};
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static inline void mxc_init_imx_uart(void)
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{
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mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
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mxc_register_device(&mxc_uart_device0, &uart_pdata);
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}
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#else /* !SERIAL_IMX */
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static inline void mxc_init_imx_uart(void)
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{
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}
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#endif /* !SERIAL_IMX */
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static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
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{
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u32 imr_val;
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u32 int_valid;
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u32 expio_irq;
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imr_val = __raw_readw(PBC_INTMASK_SET_REG);
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int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
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expio_irq = MXC_EXP_IO_BASE;
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for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
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if ((int_valid & 1) == 0)
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continue;
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generic_handle_irq(expio_irq);
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}
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}
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/*
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* Disable an expio pin's interrupt by setting the bit in the imr.
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* @param irq an expio virtual irq number
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*/
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static void expio_mask_irq(u32 irq)
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{
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u32 expio = MXC_IRQ_TO_EXPIO(irq);
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/* mask the interrupt */
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__raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
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__raw_readw(PBC_INTMASK_CLEAR_REG);
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}
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/*
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* Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
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* @param irq an expanded io virtual irq number
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*/
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static void expio_ack_irq(u32 irq)
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{
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u32 expio = MXC_IRQ_TO_EXPIO(irq);
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/* clear the interrupt status */
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__raw_writew(1 << expio, PBC_INTSTATUS_REG);
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}
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/*
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* Enable a expio pin's interrupt by clearing the bit in the imr.
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* @param irq a expio virtual irq number
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*/
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static void expio_unmask_irq(u32 irq)
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{
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u32 expio = MXC_IRQ_TO_EXPIO(irq);
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/* unmask the interrupt */
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__raw_writew(1 << expio, PBC_INTMASK_SET_REG);
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}
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static struct irq_chip expio_irq_chip = {
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.ack = expio_ack_irq,
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.mask = expio_mask_irq,
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.unmask = expio_unmask_irq,
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};
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static void __init mx31ads_init_expio(void)
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{
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int i;
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printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
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/*
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* Configure INT line as GPIO input
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*/
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mxc_iomux_setup_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
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/* disable the interrupt and clear the status */
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__raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
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__raw_writew(0xFFFF, PBC_INTSTATUS_REG);
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for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
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i++) {
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set_irq_chip(i, &expio_irq_chip);
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set_irq_handler(i, handle_level_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
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set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
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}
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#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
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/* This section defines setup for the Wolfson Microelectronics
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* 1133-EV1 PMU/audio board. When other PMU boards are supported the
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* regulator definitions may be shared with them, but for now they can
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* only be used with this board so would generate warnings about
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* unused statics and some of the configuration is specific to this
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* module.
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*/
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/* CPU */
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static struct regulator_consumer_supply sw1a_consumers[] = {
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{
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.supply = "cpu_vcc",
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}
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};
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static struct regulator_init_data sw1a_data = {
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.constraints = {
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.name = "SW1A",
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.min_uV = 1275000,
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.max_uV = 1600000,
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.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
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REGULATOR_CHANGE_MODE,
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.valid_modes_mask = REGULATOR_MODE_NORMAL |
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REGULATOR_MODE_FAST,
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.state_mem = {
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.uV = 1400000,
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.mode = REGULATOR_MODE_NORMAL,
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.enabled = 1,
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},
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.initial_state = PM_SUSPEND_MEM,
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.always_on = 1,
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.boot_on = 1,
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},
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.num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
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.consumer_supplies = sw1a_consumers,
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};
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/* System IO - High */
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static struct regulator_init_data viohi_data = {
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.constraints = {
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.name = "VIOHO",
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.min_uV = 2800000,
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.max_uV = 2800000,
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.state_mem = {
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.uV = 2800000,
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.mode = REGULATOR_MODE_NORMAL,
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.enabled = 1,
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},
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.initial_state = PM_SUSPEND_MEM,
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.always_on = 1,
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.boot_on = 1,
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},
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};
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/* System IO - Low */
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static struct regulator_init_data violo_data = {
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.constraints = {
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.name = "VIOLO",
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.min_uV = 1800000,
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.max_uV = 1800000,
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.state_mem = {
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.uV = 1800000,
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.mode = REGULATOR_MODE_NORMAL,
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.enabled = 1,
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},
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.initial_state = PM_SUSPEND_MEM,
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.always_on = 1,
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.boot_on = 1,
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},
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};
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/* DDR RAM */
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static struct regulator_init_data sw2a_data = {
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.constraints = {
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.name = "SW2A",
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.min_uV = 1800000,
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.max_uV = 1800000,
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.valid_modes_mask = REGULATOR_MODE_NORMAL,
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.state_mem = {
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.uV = 1800000,
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.mode = REGULATOR_MODE_NORMAL,
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.enabled = 1,
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},
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.state_disk = {
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.mode = REGULATOR_MODE_NORMAL,
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.enabled = 0,
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},
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.always_on = 1,
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.boot_on = 1,
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.initial_state = PM_SUSPEND_MEM,
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},
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};
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static struct regulator_init_data ldo1_data = {
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.constraints = {
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.name = "VCAM/VMMC1/VMMC2",
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.min_uV = 2800000,
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.max_uV = 2800000,
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.valid_modes_mask = REGULATOR_MODE_NORMAL,
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.apply_uV = 1,
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},
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};
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static struct regulator_consumer_supply ldo2_consumers[] = {
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{
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.supply = "AVDD",
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},
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{
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.supply = "HPVDD",
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},
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};
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/* CODEC and SIM */
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static struct regulator_init_data ldo2_data = {
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.constraints = {
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.name = "VESIM/VSIM/AVDD",
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.min_uV = 3300000,
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.max_uV = 3300000,
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.valid_modes_mask = REGULATOR_MODE_NORMAL,
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.apply_uV = 1,
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},
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.num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
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.consumer_supplies = ldo2_consumers,
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};
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/* General */
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static struct regulator_init_data vdig_data = {
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.constraints = {
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.name = "VDIG",
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.min_uV = 1500000,
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.max_uV = 1500000,
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.valid_modes_mask = REGULATOR_MODE_NORMAL,
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.apply_uV = 1,
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.always_on = 1,
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.boot_on = 1,
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},
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};
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/* Tranceivers */
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static struct regulator_init_data ldo4_data = {
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.constraints = {
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.name = "VRF1/CVDD_2.775",
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.min_uV = 2500000,
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.max_uV = 2500000,
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.valid_modes_mask = REGULATOR_MODE_NORMAL,
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.apply_uV = 1,
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.always_on = 1,
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.boot_on = 1,
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},
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};
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static struct wm8350_led_platform_data wm8350_led_data = {
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.name = "wm8350:white",
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.default_trigger = "heartbeat",
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.max_uA = 27899,
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};
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static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
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.vmid_discharge_msecs = 1000,
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.drain_msecs = 30,
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.cap_discharge_msecs = 700,
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.vmid_charge_msecs = 700,
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.vmid_s_curve = WM8350_S_CURVE_SLOW,
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.dis_out4 = WM8350_DISCHARGE_SLOW,
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.dis_out3 = WM8350_DISCHARGE_SLOW,
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.dis_out2 = WM8350_DISCHARGE_SLOW,
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.dis_out1 = WM8350_DISCHARGE_SLOW,
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.vroi_out4 = WM8350_TIE_OFF_500R,
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.vroi_out3 = WM8350_TIE_OFF_500R,
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.vroi_out2 = WM8350_TIE_OFF_500R,
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.vroi_out1 = WM8350_TIE_OFF_500R,
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.vroi_enable = 0,
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.codec_current_on = WM8350_CODEC_ISEL_1_0,
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.codec_current_standby = WM8350_CODEC_ISEL_0_5,
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.codec_current_charge = WM8350_CODEC_ISEL_1_5,
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};
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static int mx31_wm8350_init(struct wm8350 *wm8350)
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{
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int i;
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wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
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WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
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WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
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WM8350_GPIO_DEBOUNCE_ON);
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wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
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WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
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WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
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WM8350_GPIO_DEBOUNCE_ON);
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wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
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WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
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WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
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WM8350_GPIO_DEBOUNCE_OFF);
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wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
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WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
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WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
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WM8350_GPIO_DEBOUNCE_OFF);
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wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
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WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
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WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
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WM8350_GPIO_DEBOUNCE_OFF);
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wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
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WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
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WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
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WM8350_GPIO_DEBOUNCE_OFF);
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wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
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WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
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WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
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WM8350_GPIO_DEBOUNCE_OFF);
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/* Fix up for our own supplies. */
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for (i = 0; i < ARRAY_SIZE(ldo2_consumers); i++)
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ldo2_consumers[i].dev = wm8350->dev;
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wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
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wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
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wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
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wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
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wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
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wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
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wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
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wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
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/* LEDs */
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wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
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WM8350_DC5_ERRACT_SHUTDOWN_CONV);
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wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
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WM8350_ISINK_FLASH_DISABLE,
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WM8350_ISINK_FLASH_TRIG_BIT,
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WM8350_ISINK_FLASH_DUR_32MS,
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WM8350_ISINK_FLASH_ON_INSTANT,
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WM8350_ISINK_FLASH_OFF_INSTANT,
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WM8350_ISINK_FLASH_MODE_EN);
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wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
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WM8350_ISINK_MODE_BOOST,
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WM8350_ISINK_ILIM_NORMAL,
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WM8350_DC5_RMP_20V,
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WM8350_DC5_FBSRC_ISINKA);
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wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
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&wm8350_led_data);
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wm8350->codec.platform_data = &imx32ads_wm8350_setup;
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regulator_has_full_constraints();
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|
|
return 0;
|
|
}
|
|
|
|
static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
|
|
.init = mx31_wm8350_init,
|
|
};
|
|
#endif
|
|
|
|
#if defined(CONFIG_I2C_IMX) || defined(CONFIG_I2C_IMX_MODULE)
|
|
static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
|
|
#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
|
|
{
|
|
I2C_BOARD_INFO("wm8350", 0x1a),
|
|
.platform_data = &mx31_wm8350_pdata,
|
|
.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
|
|
},
|
|
#endif
|
|
};
|
|
|
|
static void mxc_init_i2c(void)
|
|
{
|
|
i2c_register_board_info(1, mx31ads_i2c1_devices,
|
|
ARRAY_SIZE(mx31ads_i2c1_devices));
|
|
|
|
mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
|
|
mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
|
|
|
|
mxc_register_device(&mxc_i2c_device1, NULL);
|
|
}
|
|
#else
|
|
static void mxc_init_i2c(void)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
/*!
|
|
* This structure defines static mappings for the i.MX31ADS board.
|
|
*/
|
|
static struct map_desc mx31ads_io_desc[] __initdata = {
|
|
{
|
|
.virtual = SPBA0_BASE_ADDR_VIRT,
|
|
.pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
|
|
.length = SPBA0_SIZE,
|
|
.type = MT_DEVICE_NONSHARED
|
|
}, {
|
|
.virtual = CS4_BASE_ADDR_VIRT,
|
|
.pfn = __phys_to_pfn(CS4_BASE_ADDR),
|
|
.length = CS4_SIZE / 2,
|
|
.type = MT_DEVICE
|
|
},
|
|
};
|
|
|
|
/*!
|
|
* Set up static virtual mappings.
|
|
*/
|
|
static void __init mx31ads_map_io(void)
|
|
{
|
|
mx31_map_io();
|
|
iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
|
|
}
|
|
|
|
static void __init mx31ads_init_irq(void)
|
|
{
|
|
mxc_init_irq();
|
|
mx31ads_init_expio();
|
|
}
|
|
|
|
/*!
|
|
* Board specific initialization.
|
|
*/
|
|
static void __init mxc_board_init(void)
|
|
{
|
|
mxc_init_extuart();
|
|
mxc_init_imx_uart();
|
|
mxc_init_i2c();
|
|
}
|
|
|
|
static void __init mx31ads_timer_init(void)
|
|
{
|
|
mx31_clocks_init(26000000);
|
|
}
|
|
|
|
static struct sys_timer mx31ads_timer = {
|
|
.init = mx31ads_timer_init,
|
|
};
|
|
|
|
/*
|
|
* The following uses standard kernel macros defined in arch.h in order to
|
|
* initialize __mach_desc_MX31ADS data structure.
|
|
*/
|
|
MACHINE_START(MX31ADS, "Freescale MX31ADS")
|
|
/* Maintainer: Freescale Semiconductor, Inc. */
|
|
.phys_io = AIPS1_BASE_ADDR,
|
|
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
|
|
.boot_params = PHYS_OFFSET + 0x100,
|
|
.map_io = mx31ads_map_io,
|
|
.init_irq = mx31ads_init_irq,
|
|
.init_machine = mxc_board_init,
|
|
.timer = &mx31ads_timer,
|
|
MACHINE_END
|