e79b76e03b
Currently Monitor Mode Control Registers and Sampling registers are part of extended regs. Patch adds support to include Performance Monitor Counter Registers (PMC1 to PMC6 ) as part of extended registers. PMCs are saved in the perf interrupt handler as part of per-cpu array 'pmcs' in struct cpu_hw_events. While capturing the register values for extended regs, fetch these saved PMC values. Simplified the PERF_REG_PMU_MASK_300/31 definition to include PMU SPRs MMCR0 to PMC6. Exclude the unsupported SPRs (MMCR3, SIER2, SIER3) from extended mask value for CPU_FTR_ARCH_300 in the new definition. PERF_REG_EXTENDED_MAX is used to check if any index beyond the extended registers is requested in the sample. Have one PERF_REG_EXTENDED_MAX for CPU_FTR_ARCH_300/CPU_FTR_ARCH_31 since perf_reg_validate function already checks the extended mask for the presence of any unsupported register. Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/1612335337-1888-3-git-send-email-atrajeev@linux.vnet.ibm.com
148 lines
4.5 KiB
C
148 lines
4.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2016 Anju T, IBM Corporation.
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*/
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/sched/task_stack.h>
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#include <linux/perf_event.h>
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#include <linux/bug.h>
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#include <linux/stddef.h>
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#include <asm/ptrace.h>
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#include <asm/perf_regs.h>
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u64 PERF_REG_EXTENDED_MASK;
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#define PT_REGS_OFFSET(id, r) [id] = offsetof(struct pt_regs, r)
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#define REG_RESERVED (~(PERF_REG_EXTENDED_MASK | PERF_REG_PMU_MASK))
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static unsigned int pt_regs_offset[PERF_REG_POWERPC_MAX] = {
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PT_REGS_OFFSET(PERF_REG_POWERPC_R0, gpr[0]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R1, gpr[1]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R2, gpr[2]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R3, gpr[3]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R4, gpr[4]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R5, gpr[5]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R6, gpr[6]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R7, gpr[7]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R8, gpr[8]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R9, gpr[9]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R10, gpr[10]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R11, gpr[11]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R12, gpr[12]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R13, gpr[13]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R14, gpr[14]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R15, gpr[15]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R16, gpr[16]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R17, gpr[17]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R18, gpr[18]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R19, gpr[19]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R20, gpr[20]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R21, gpr[21]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R22, gpr[22]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R23, gpr[23]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R24, gpr[24]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R25, gpr[25]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R26, gpr[26]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R27, gpr[27]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R28, gpr[28]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R29, gpr[29]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R30, gpr[30]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_R31, gpr[31]),
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PT_REGS_OFFSET(PERF_REG_POWERPC_NIP, nip),
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PT_REGS_OFFSET(PERF_REG_POWERPC_MSR, msr),
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PT_REGS_OFFSET(PERF_REG_POWERPC_ORIG_R3, orig_gpr3),
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PT_REGS_OFFSET(PERF_REG_POWERPC_CTR, ctr),
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PT_REGS_OFFSET(PERF_REG_POWERPC_LINK, link),
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PT_REGS_OFFSET(PERF_REG_POWERPC_XER, xer),
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PT_REGS_OFFSET(PERF_REG_POWERPC_CCR, ccr),
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#ifdef CONFIG_PPC64
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PT_REGS_OFFSET(PERF_REG_POWERPC_SOFTE, softe),
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#else
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PT_REGS_OFFSET(PERF_REG_POWERPC_SOFTE, mq),
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#endif
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PT_REGS_OFFSET(PERF_REG_POWERPC_TRAP, trap),
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PT_REGS_OFFSET(PERF_REG_POWERPC_DAR, dar),
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PT_REGS_OFFSET(PERF_REG_POWERPC_DSISR, dsisr),
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PT_REGS_OFFSET(PERF_REG_POWERPC_SIER, dar),
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PT_REGS_OFFSET(PERF_REG_POWERPC_MMCRA, dsisr),
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};
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/* Function to return the extended register values */
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static u64 get_ext_regs_value(int idx)
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{
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switch (idx) {
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case PERF_REG_POWERPC_PMC1 ... PERF_REG_POWERPC_PMC6:
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return get_pmcs_ext_regs(idx - PERF_REG_POWERPC_PMC1);
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case PERF_REG_POWERPC_MMCR0:
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return mfspr(SPRN_MMCR0);
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case PERF_REG_POWERPC_MMCR1:
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return mfspr(SPRN_MMCR1);
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case PERF_REG_POWERPC_MMCR2:
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return mfspr(SPRN_MMCR2);
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#ifdef CONFIG_PPC64
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case PERF_REG_POWERPC_MMCR3:
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return mfspr(SPRN_MMCR3);
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case PERF_REG_POWERPC_SIER2:
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return mfspr(SPRN_SIER2);
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case PERF_REG_POWERPC_SIER3:
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return mfspr(SPRN_SIER3);
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#endif
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default: return 0;
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}
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}
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u64 perf_reg_value(struct pt_regs *regs, int idx)
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{
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if (idx == PERF_REG_POWERPC_SIER &&
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(IS_ENABLED(CONFIG_FSL_EMB_PERF_EVENT) ||
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IS_ENABLED(CONFIG_PPC32) ||
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!is_sier_available()))
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return 0;
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if (idx == PERF_REG_POWERPC_MMCRA &&
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(IS_ENABLED(CONFIG_FSL_EMB_PERF_EVENT) ||
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IS_ENABLED(CONFIG_PPC32)))
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return 0;
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if (idx >= PERF_REG_POWERPC_MAX && idx < PERF_REG_EXTENDED_MAX)
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return get_ext_regs_value(idx);
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/*
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* If the idx is referring to value beyond the
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* supported registers, return 0 with a warning
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*/
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if (WARN_ON_ONCE(idx >= PERF_REG_EXTENDED_MAX))
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return 0;
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return regs_get_register(regs, pt_regs_offset[idx]);
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}
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int perf_reg_validate(u64 mask)
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{
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if (!mask || mask & REG_RESERVED)
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return -EINVAL;
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return 0;
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}
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u64 perf_reg_abi(struct task_struct *task)
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{
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#ifdef CONFIG_PPC64
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if (!test_tsk_thread_flag(task, TIF_32BIT))
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return PERF_SAMPLE_REGS_ABI_64;
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else
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#endif
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return PERF_SAMPLE_REGS_ABI_32;
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}
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void perf_get_regs_user(struct perf_regs *regs_user,
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struct pt_regs *regs)
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{
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regs_user->regs = task_pt_regs(current);
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regs_user->abi = (regs_user->regs) ? perf_reg_abi(current) :
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PERF_SAMPLE_REGS_ABI_NONE;
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}
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