forked from Minki/linux
267 lines
7.5 KiB
C
267 lines
7.5 KiB
C
/*
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*
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* Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
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* Copied and modified Carsten Langgaard's time.c
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*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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* Setting up the clock on the MIPS boards.
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*
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* We provide the clock interrupt processing and the timer offset compute
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* functions. If CONFIG_PM is selected, we also ensure the 32KHz timer is
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* available. -- Dan
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <asm/mipsregs.h>
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#include <asm/time.h>
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#include <asm/mach-au1x00/au1000.h>
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static int no_au1xxx_32khz;
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extern int allow_au1k_wait; /* default off for CP0 Counter */
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#ifdef CONFIG_PM
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#if HZ < 100 || HZ > 1000
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#error "unsupported HZ value! Must be in [100,1000]"
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#endif
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#define MATCH20_INC (328 * 100 / HZ) /* magic number 328 is for HZ=100... */
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static unsigned long last_pc0, last_match20;
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#endif
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static DEFINE_SPINLOCK(time_lock);
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unsigned long wtimer;
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#ifdef CONFIG_PM
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static irqreturn_t counter0_irq(int irq, void *dev_id)
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{
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unsigned long pc0;
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int time_elapsed;
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static int jiffie_drift;
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if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
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/* should never happen! */
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printk(KERN_WARNING "counter 0 w status error\n");
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return IRQ_NONE;
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}
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pc0 = au_readl(SYS_TOYREAD);
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if (pc0 < last_match20)
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/* counter overflowed */
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time_elapsed = (0xffffffff - last_match20) + pc0;
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else
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time_elapsed = pc0 - last_match20;
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while (time_elapsed > 0) {
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do_timer(1);
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#ifndef CONFIG_SMP
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update_process_times(user_mode(get_irq_regs()));
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#endif
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time_elapsed -= MATCH20_INC;
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last_match20 += MATCH20_INC;
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jiffie_drift++;
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}
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last_pc0 = pc0;
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au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
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au_sync();
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/*
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* Our counter ticks at 10.009765625 ms/tick, we we're running
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* almost 10 uS too slow per tick.
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*/
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if (jiffie_drift >= 999) {
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jiffie_drift -= 999;
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do_timer(1); /* increment jiffies by one */
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#ifndef CONFIG_SMP
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update_process_times(user_mode(get_irq_regs()));
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#endif
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}
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return IRQ_HANDLED;
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}
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struct irqaction counter0_action = {
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.handler = counter0_irq,
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.flags = IRQF_DISABLED,
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.name = "alchemy-toy",
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.dev_id = NULL,
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};
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/* When we wakeup from sleep, we have to "catch up" on all of the
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* timer ticks we have missed.
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*/
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void wakeup_counter0_adjust(void)
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{
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unsigned long pc0;
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int time_elapsed;
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pc0 = au_readl(SYS_TOYREAD);
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if (pc0 < last_match20)
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/* counter overflowed */
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time_elapsed = (0xffffffff - last_match20) + pc0;
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else
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time_elapsed = pc0 - last_match20;
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while (time_elapsed > 0) {
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time_elapsed -= MATCH20_INC;
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last_match20 += MATCH20_INC;
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}
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last_pc0 = pc0;
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au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
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au_sync();
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}
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/* This is just for debugging to set the timer for a sleep delay. */
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void wakeup_counter0_set(int ticks)
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{
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unsigned long pc0;
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pc0 = au_readl(SYS_TOYREAD);
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last_pc0 = pc0;
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au_writel(last_match20 + (MATCH20_INC * ticks), SYS_TOYMATCH2);
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au_sync();
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}
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#endif
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/*
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* I haven't found anyone that doesn't use a 12 MHz source clock,
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* but just in case.....
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*/
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#define AU1000_SRC_CLK 12000000
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/*
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* We read the real processor speed from the PLL. This is important
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* because it is more accurate than computing it from the 32 KHz
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* counter, if it exists. If we don't have an accurate processor
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* speed, all of the peripherals that derive their clocks based on
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* this advertised speed will introduce error and sometimes not work
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* properly. This function is futher convoluted to still allow configurations
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* to do that in case they have really, really old silicon with a
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* write-only PLL register, that we need the 32 KHz when power management
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* "wait" is enabled, and we need to detect if the 32 KHz isn't present
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* but requested......got it? :-) -- Dan
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*/
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unsigned long calc_clock(void)
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{
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unsigned long cpu_speed;
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unsigned long flags;
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unsigned long counter;
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spin_lock_irqsave(&time_lock, flags);
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/* Power management cares if we don't have a 32 KHz counter. */
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no_au1xxx_32khz = 0;
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counter = au_readl(SYS_COUNTER_CNTRL);
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if (counter & SYS_CNTRL_E0) {
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int trim_divide = 16;
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au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL);
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while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
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/* RTC now ticks at 32.768/16 kHz */
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au_writel(trim_divide - 1, SYS_RTCTRIM);
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while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
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while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
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au_writel(0, SYS_TOYWRITE);
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while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
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} else
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no_au1xxx_32khz = 1;
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/*
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* On early Au1000, sys_cpupll was write-only. Since these
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* silicon versions of Au1000 are not sold by AMD, we don't bend
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* over backwards trying to determine the frequency.
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*/
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if (cur_cpu_spec[0]->cpu_pll_wo)
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#ifdef CONFIG_SOC_AU1000_FREQUENCY
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cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;
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#else
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cpu_speed = 396000000;
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#endif
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else
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cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
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/* On Alchemy CPU:counter ratio is 1:1 */
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mips_hpt_frequency = cpu_speed;
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/* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */
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set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)
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& 0x03) + 2) * 16));
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spin_unlock_irqrestore(&time_lock, flags);
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return cpu_speed;
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}
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void __init plat_time_init(void)
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{
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unsigned int est_freq = calc_clock();
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est_freq += 5000; /* round */
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est_freq -= est_freq%10000;
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printk(KERN_INFO "CPU frequency %u.%02u MHz\n",
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est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000);
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set_au1x00_speed(est_freq);
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set_au1x00_lcd_clock(); /* program the LCD clock */
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#ifdef CONFIG_PM
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/*
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* setup counter 0, since it keeps ticking after a
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* 'wait' instruction has been executed. The CP0 timer and
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* counter 1 do NOT continue running after 'wait'
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*
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* It's too early to call request_irq() here, so we handle
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* counter 0 interrupt as a special irq and it doesn't show
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* up under /proc/interrupts.
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*
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* Check to ensure we really have a 32 KHz oscillator before
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* we do this.
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*/
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if (no_au1xxx_32khz)
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printk(KERN_WARNING "WARNING: no 32KHz clock found.\n");
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else {
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while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
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au_writel(0, SYS_TOYWRITE);
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while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
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au_writel(au_readl(SYS_WAKEMSK) | (1 << 8), SYS_WAKEMSK);
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au_writel(~0, SYS_WAKESRC);
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au_sync();
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while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
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/* Setup match20 to interrupt once every HZ */
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last_pc0 = last_match20 = au_readl(SYS_TOYREAD);
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au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
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au_sync();
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while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
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setup_irq(AU1000_TOY_MATCH2_INT, &counter0_action);
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/* We can use the real 'wait' instruction. */
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allow_au1k_wait = 1;
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}
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#endif
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}
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